SPI MISO data bus empty on logic Analyser

RE: SPI MISO data bus empty on logic Analyser

vw_dev — Thu, 09 Jun 2022 13:53:31 GMT

Hello,

I solved the issue. It was at a hardware level:

I am using a demo circuit implementing the LTC6804 which output is in isoSPI. I added a isoSPI/SPI interface and then connected it with a breadboard to the nrf52832. I also removed my pull-ups and it is working fine.

The MOSI channel is sending the right frames and the MISO is responding only after the MOSI frames with the correct values. It was not because the logic analyser were not configured correctly.

Thank you for your help!

RE: SPI MISO data bus empty on logic Analyser

Jared — Wed, 08 Jun 2022 12:43:25 GMT

Something is obviously not correct here, it's either the logic analyzer not configured correctly or the slave. Can you flash the chip with the nrfx SPI example from the SDK and see if the data is duplicated on MISO?

RE: SPI MISO data bus empty on logic Analyser

vw_dev — Wed, 01 Jun 2022 11:50:43 GMT

What I find strange is that on a normal SPI communication, the response on the MISO bus should be after receiving the command frames, which is not the case here.

The logic analyser is only displaying what data go through the bus, right? So I don't know if the issue is starting from here

RE: SPI MISO data bus empty on logic Analyser

vw_dev — Wed, 01 Jun 2022 11:48:29 GMT

Hello,

Thank you for your answer.

The slave is configured so that when it receive commands frames, it would respond automatically. I only changed the physical jumpers to disable isoSPI communication and enable SPI communication.

On the slave board, the uC used is the LTC6804-1, which is indeed daisy-chainable. I know that the slave is also configured so that it transmits the data to a external uC as the nRF. I am only using one slave, so I assumed that the slave would respond only after receiving command frames.

RE: SPI MISO data bus empty on logic Analyser

Jared — Wed, 01 Jun 2022 10:05:34 GMT

fair point, vw_dev could you double check this?

RE: SPI MISO data bus empty on logic Analyser

hmolesworth — Tue, 31 May 2022 15:51:41 GMT

The picture shows a different waveform on MISO to that on MOSI, which is to be expected and might even be correct. The decode above MISO on the picture seems to indicate the logic analyser has been set to decode MOSI on both traces instead of MISO on the 2nd trace

RE: SPI MISO data bus empty on logic Analyser

Jared — Tue, 31 May 2022 13:30:11 GMT

Hi,

[quote user=""]I am communicating with it through SPI and sending it the trams of commands necessay to read the voltage of the cells. Through a logic Analyser, I see that I am sending the correct frames on the MOSI bus, the clock is working fine and the Channel Select aswell.[/quote]

Usually, this would indicate that the issue relies with the slave. If the output from the nRF really is correct then the slave should respond as described in the datasheet, if it doesn't then maybe the slave isn't configured correctly according to its datasheet?

[quote user="vw_dev"]

Now it seems that the data in the MISO bus is the same as the MOSI's as shown in the picture. But no traces of the response... Can you help me with that?

Thank you

[/quote]

Given the datasheet of the LTC6804-2 a quick read, I saw that the device has the option of daisy chaining. Which would explain why it's replicating the data that is sent on MOSI onto MISO. Most likely the slave is configured to be SPI master for daisy chaining, I suggest that you doublecheck the datasheet and verify if it's configured correct or not. Also the internal pull-up on the nRF is 13k.

regards

Jared

RE: SPI MISO data bus empty on logic Analyser

vw_dev — Tue, 31 May 2022 08:24:22 GMT

Thank for the answer!

I added in my setup a pull-up resistor powered by the VDD of the DK, on every SPI buses, and I configured in the sdk_config.h :

NRF_SPI_DRV_MISO_PULLUP_CFG 3

Which configure the MISO GPIO pin into pull-up.

Now it seems that the data in the MISO bus is the same as the MOSI's as shown in the picture. But no traces of the response... Can you help me with that?

Thank you

RE: SPI MISO data bus empty on logic Analyser

hmolesworth — Mon, 30 May 2022 23:35:24 GMT

I think MISO should be high - regardless of whether the PEC is calculated correctly - when a tx frame from the host nRF52 is started; since it is shown as low on the logic analyser this implies there is no pull-up fitted (pedantic: or no pin connection or incorrect nRF52 pin config or pin short to ground):

"Connecting ISOMD to V– configures serial Port A for 4-wire SPI. The SDO pin is an open drain output which requires a pull-up resistor tied to the appropriate supply voltage"