SPIS Multi-Byte Read/Write (Burst-Mode)

RE: SPIS Multi-Byte Read/Write (Burst-Mode)

Håkon Alseth — Wed, 29 Jun 2022 14:07:31 GMT

Hi,

[quote user="Talisca"]To my understanding, as long as the master sends the next 8 clock pulses, the slave should receive the next byte. As long as it does not take too long (hence the timeout).[/quote]

The problem is that once the CSN is latched, your buffers are locked. You shall not change the content of the memory at this point.

CSN input is controlled by the hardware, so there's not many ways around this, other than to send and receive in two separate SPI transactions. See this chapter specifically: https://infocenter.nordicsemi.com/topic/ps_nrf52840/spis.html?cp=4_0_0_5_25_2#concept_abk_lbf_wr

Kind regards,

Håkon

RE: SPIS Multi-Byte Read/Write (Burst-Mode)

Talisca — Wed, 29 Jun 2022 13:00:04 GMT

Thank you very much for the answer.

That is relatively clear to me. What I want to achieve is the following:
In the nRF52840 I manage a so-called register of n bytes. For demonstration purposes, let's just define 64 bytes for this.
I want to make this register available via SPI. So a master should be able to write and read data here arbitrarily.

Classically each byte is addressed by a register address. This is usually done by the first byte sent by the master.
The highest bit of this byte corresponds to a read/write flag. If this bit is set (0b10000000) then the master wants to read from the specified address. Otherwise he wants to write data to the address.

If the master now writes 0x00 as the first byte, as a slave I know: Okay, the master wants to write into the register with the address 0x00.
So the next byte sent by the master is the data.
The same is true for all further addresses up to 0x3F.

Now I know of many devices that implement a protocol to write or read multiple bytes in one burst. For this the device performs an internal auto-increment of the address with every further received or written byte.
So instead of the master having to establish a new communication and send the address every time like:

tx_buffer[0] = 0x00u; // Register-Address 0x00
tx_buffer[1] = 0xAAu; // Data for Register-Address 0x00
spi_write(spi_dev, &spi_cfg, &tx);

tx_buffer[0] = 0x01u; // Register-Address 0x01
tx_buffer[1] = 0x42u; // Data for Register-Address 0x01
spi_write(spi_dev, &spi_cfg, &tx);

Instead, I would like to do this in one go:

tx_buffer[0] = 0x00u; // Register-Address 0x00
tx_buffer[1] = 0xAAu; // Data for Register-Address 0x00
tx_buffer[2] = 0x42u; // Data for Register-Address 0x01
spi_write(spi_dev, &spi_cfg, &tx);

So as in my slave example code in my previous post, I would expect something like this to work:

spi_read(spi_dev, &spi_cfg, &rx); // Read one byte as start-address
current_address = rx_buffer[0];
do
{
	spi_read(spi_dev, &spi_cfg, &rx); // Read next data byte 
	my_registers[current_address++] = rx_buffer[0]; // write data into current register address and increment address itself
}while(no timeout and other conditions);

To my understanding, as long as the master sends the next 8 clock pulses, the slave should receive the next byte. As long as it does not take too long (hence the timeout).

Another example would be this description (taken from ISM330DLC Datasheet)

https://imgur.com/a/8v3R1Nb

RE: SPIS Multi-Byte Read/Write (Burst-Mode)

Håkon Alseth — Wed, 29 Jun 2022 12:15:32 GMT

Hi,

I'm a bit uncertain in the feature that you're after here, please explain a bit more in-detail if I've misunderstood anything.

Writing to the tx_buf / rx_buf structs does not automatically trigger a transaction. The nRF52840 does not have a generic DMA channel, if that is the functionality you're after.

Let us define a transaction as CSN going active, x bytes clock in, and CSN goes inactive.

The SPIS cannot dynamically change the content based on the first byte within the same transaction. Each transaction must be decided upon prior to when CSN goes active.

The SPIS peripheral works as described in the PS:

https://infocenter.nordicsemi.com/topic/ps_nrf52840/spis.html?cp=4_0_0_5_25

After writing your data to the respective struct, you'll have to trigger a transfer function (which sets up the easydma buffers and starts the transfer), as shown in this SPIM example:

https://github.com/sigurdnev/ncs-playground/blob/master/samples/spi_test/src/main.c

(there's also spis samples in the above repo)

Kind regards,

Håkon