NETCPU timer interrupt issues

RE: NETCPU timer interrupt issues

Kenneth — Mon, 25 Jul 2022 12:28:38 GMT

[quote user="peran"]but are you saying that interrupts are not available on capture, and that my interrupts are generated from a compare match on the captured value? [/quote]

Yes, the intention is simply something like:

NRF_TIMER->TASKS_CAPTURE[0] = 1;
return NRF_TIMER->CC[0];

RE: NETCPU timer interrupt issues

peran — Mon, 25 Jul 2022 11:55:28 GMT

Reg capture and interrupt. I am not 100% sure I understand, but are you saying that interrupts are not available on capture, and that my interrupts are generated from a compare match on the captured value?

I'll check out the EGU.

RE: NETCPU timer interrupt issues

Kenneth — Mon, 25 Jul 2022 10:52:14 GMT

Hi again,

[quote user="peran"]But surely the interrupt is supposed to also trigger on a capture? There are so many cases where you want to capture something _and_ be notified about it. It does trigger on timer2, so that indicates that this functionality is available.[/quote]

I see your point, but I would not rely on this, since by the time you update CC register the counter value might have incremented at the same time, so I expect there will be corner cases here where there is no interrupt from this operation. If you need an interrupt, you may trigger the EGU interrupt instead (which can trigger an event that also can be used to trigger capture on both timers if you want):
https://infocenter.nordicsemi.com/topic/ps_nrf5340/egu.html

[quote user="peran"]Could this ticket be transferred to someone who is not vacationing? I appreciate that it is summer holidays, but it's been 17 days since I submitted, and counting another 21 it will be 38 days without anything more than scratching the surface of my issue.[/quote]

I see your point here also, the problem the last 2 weeks have been low staff due to vacation, the next 2 and half week I am taking my vacation. But I can see if someone can fill in next week where there are more people back.

Best regards,
Kenneth

RE: NETCPU timer interrupt issues

peran — Mon, 25 Jul 2022 10:22:24 GMT

Regarding double MS_TIMER EVENTS clearing, yes that is an oversight. But it is the ISR that uses MS_TIMER, so it does not matter if I clear it twice. I have amended my example, and attached it again.

No, there is no check for which compare. As long as my issue is that the interrupts don't fire properly, I don't care about which CC. This code is an example to reproduce the issue in the simplest way, not my production code. This is also why I execute the capture task from main. I am sure the result would be the same if I used e.g. a work-queue, or routed the signal via IPC and DPPI from the appcore.

Regarding Capture interrupt. You say that the task doesn't trigger the interrupt, and I see that the INTENSET register says "compare." But surely the interrupt is supposed to also trigger on a capture? There are so many cases where you want to capture something _and_ be notified about it. It does trigger on timer2, so that indicates that this functionality is available.

Could this ticket be transferred to someone who is not vacationing? I appreciate that it is summer holidays, but it's been 17 days since I submitted, and counting another 21 it will be 38 days without anything more than scratching the surface of my issue.

devzone.nordicsemi.com/.../blinky2.zip

RE: NETCPU timer interrupt issues

Kenneth — Mon, 25 Jul 2022 09:32:40 GMT

I will likely not have time to look into this until I am back from vacation in about 3 weeks time.

I did quickly glance at the blinky example you provided, I found it a bit strange that you in your isr2 cleared both MS_TIMER and US_TIMER EVENTS_COMPARE event, while in isr1 you cleared MS_TIMER EVENTS_COMPARE two times.

There is no check in your isr handlers to check which compare event triggered the interrupt, and you should only need to clear the event for the timer that triggered the interrupt before you exit the interrupt handler.

I notice you are executing capture tasks in main, if you need those to execute straight after eachother I would recommend that you add a disable/enable interrupts around them. If not you can get some race condition where there is an interrupt between the two. The capture task doesn't trigger the interrupt, it only copy the timer's count value to the corresponding CC register.

Best regards,
Kenneth

RE: NETCPU timer interrupt issues

peran — Mon, 25 Jul 2022 08:27:48 GMT

Hi,

Any update on this? Did anyone test my code?

RE: NETCPU timer interrupt issues

peran — Mon, 18 Jul 2022 07:56:19 GMT

I recorded 900 secs of pin toggling. I got 40283 toggles from the event, and 40240 toggles from the interrupt, meaning I have 43 missing interrupts.

RE: NETCPU timer interrupt issues

peran — Mon, 18 Jul 2022 07:28:55 GMT

A little update: I have found another timer interrupt issue:

The screenshot shows two pins toggling. The bottom is toggling via GPIOTE, using the aforementioned APPCPU-IPC-DPPi-channel. This is the same signal that triggers the capture and thus initiaties the CC-interrupt. The top is a pin being toggled inside the interrupt. As you can see there are two events that don't lead to an interrupt. I don't have hard numbers right now, but this happens frequently, so it is a serious issue. I will do a more thorough test on the frequency today.

Time between edges are approx 21ms.

RE: NETCPU timer interrupt issues

peran — Tue, 12 Jul 2022 10:40:10 GMT

I will, but I am currently working my way around it. With the DK example I feel I can be pretty sure that it is not my code that is the issue, and that I need nordic to look into the design and tell me why I am seeing this undocumented/errata-ish behaviour. Both regarding the missing IRQ and the need to clear CC reg on CC interrupt.

RE: NETCPU timer interrupt issues

Kenneth — Tue, 12 Jul 2022 09:17:40 GMT

Due to many are on summer holiday I am not sure when I will have time to look into this, but it's on my todo list. Let me know if you have new findings.

Kenneth

RE: NETCPU timer interrupt issues

peran — Mon, 11 Jul 2022 16:06:44 GMT

Marking on chip is QKAA0D 2106AF. The DK I used for the example also has same markings, last line is 2122AH. I use NCS 1.7.0.

RE: NETCPU timer interrupt issues

Kenneth — Mon, 11 Jul 2022 15:58:33 GMT

Hi,

I will try to replicate this, but just to make sure we are not overlooking anything here, can you provide details of the chip markings printed on the nRF5340 chip? I just want to make sure you are using the massproduction version, and not have received some early engineering samples before the chip was qualified. Also, please provide details of which NCS version the example is based on.

Kenneth

RE: NETCPU timer interrupt issues

peran — Mon, 11 Jul 2022 13:59:14 GMT

I'm using custom hw.

I've created a quick example for NRF5340dk, which modifies the blinky example from zephyr. Please see how only one led blinks. By removing/toggling TIMERn->TASKS_CAPTURE in the main function you can change the behaviour.There is also terminal output you can look at.

Please also note that you need to write the CC reg in the ISR to clear the interrupt. This is not documented in the DS afaik.

devzone.nordicsemi.com/.../0523.blinky.zip

RE: NETCPU timer interrupt issues

Kenneth — Mon, 11 Jul 2022 12:58:43 GMT

Can you provide label of the nRF5340-DK you are using?

Kenneth

RE: NETCPU timer interrupt issues

peran — Mon, 11 Jul 2022 12:35:46 GMT

No, my last comment is not a fix, it was simply about your readability.

Even if I remove the IPC/DPPI stuff for triggering the interrupt, and do a NRF_TIMER1->TASKS_CAPTURE[n] the interrupt will only run execute for TIMER2. I've also tried to run it in normal mode (not counter mode) and without the DPPI chaining of timers.

I also checked the relevant isr_tables.c to see that my ISR is included.

Any ideas as to next steps?

RE: NETCPU timer interrupt issues

Kenneth — Mon, 11 Jul 2022 11:01:29 GMT

I am not aware of any issue with the hardware timers that should explain why they behave differently, based on your last comment I think you might have found the problem.

Kenneth

RE: NETCPU timer interrupt issues

peran — Fri, 08 Jul 2022 12:27:38 GMT

I did some renaming in the code to make it more readable, and immediately noticed one oversight: HS_TIMER is TIMER2.