RE: How to reduce spi chipselect to sclk delay

Abdullah Zaman — Tue, 26 Jul 2022 09:09:17 GMT

Hi Kenneth,

I was able to resolve this issue by using nrfx driver and spi instance 4. Thanks for your help

RE: How to reduce spi chipselect to sclk delay

Kenneth — Wed, 20 Jul 2022 12:18:46 GMT

I do remember I looked into this some time ago, and found the same. There is a delay between CSN to CLK, and it's just due to the way it's implemented when being used by zephyr. In general though having a delay of ~5-10us can be a good idea, since some peers also need to wakeup before they can receive data.

That said though, if you want to reduce this time, then the best (or only way) would be to look at using SPIM instance 4, which have CSNDUR register that can control this timing: https://infocenter.nordicsemi.com/topic/ps_nrf5340/spim.html#topic It's only SPIM instance 4 that support direct control over CSN pin directly be the SPIM perpiheral.

Kenneth