Pull-up circuit on nReset (P0.21) malfunctioning?

RE: Pull-up circuit on nReset (P0.21) malfunctioning?

Kenneth — Wed, 31 Aug 2022 06:57:49 GMT

Thanks for sharing measurement, VDD rise time is good, but it's indeed something suspicious about the voltage on nreset, not something I have seen earlier. Based on your current description and fix I don't think it's anything faulty with the nRF52832, so I don't see a need to transfer this case to QA and ask for an RMA to return samples here for ATE retest. If you later find samples that are permantely stuck in reset or other symptoms please let us know (and possible with a link to this case) so we may follow up.

Kenneth

RE: Pull-up circuit on nReset (P0.21) malfunctioning?

Konrad Hammel — Tue, 30 Aug 2022 20:53:37 GMT

Thanks for the replies!

We have removed power from the failing samples for over 1 minute (several days to weeks for some samples) and the issue persists.

Vdd waveform from a good sample (bad sample is the same):

nreset waveform for a good sample:

nreset waveform for a bad sample:

At this time we consider the issue to be caused by a faulty capacitor.

In future builds we will remove the circuit and disable the reset pin in firmware.

RE: Pull-up circuit on nReset (P0.21) malfunctioning?

Kenneth — Mon, 15 Aug 2022 12:22:12 GMT

Hi,

I am not aware of any issue that may explain this no, trying the two experiments (remove capacitor and/or bake board) suggested by hmolesworth should be useful.

Do you by any chance have a board that still fails? Could you provide a oscilloscope plot of the VDD and nRESET when power is applied? I am slightly interested if the rise time may tell us anything.

Best regards,
Kenneth

RE: Pull-up circuit on nReset (P0.21) malfunctioning?

hmolesworth — Fri, 12 Aug 2022 23:32:23 GMT

If the 100nF capacitor to Gnd has become leaky then the use of a hot-air gun close by to remove and replace the pull-up resistor may indicate that moisture absorption or other contamination of the capacitor may be an issue. Both hot-air (very likely) and increased current through the leak (tweezer short) (less likely) can affect this. Perhaps try removing the reset pin capacitor on all the problem boards and see how many recover. That reset capacitor is not necessary, unless there are very high levels of radiated or coupled noise, which is unlikely without other issues arising. Moisture or leakage on the pull-up would be irrelevant, and the pull-up is not really required given the internal pull-up enabled when the pin is used as a reset pin. Baking a faulty board is another test which would indicate contamination should the board recover.

A leaky internal schottky protection diode to Gnd could also be an issue - caused by an ESD event - but in that case the two steps noted above would not correct the problem as the schottky leak would likely be permanent.

2.3 is 70% of 3.4, ie the switching threshold of the internal FET; a failed gate could do this, but that would not recover as in the two steps noted above.

Nordic engineers will help with errata (known and unreported), I am not aware of anything specific other than it has been reported that malfunctioning firmware can drive a reset pin low leading to permanent reset oscillation (I have not tested this). Maybe see nreset-pin-specifications.

Having a reset pin enabled adds another single-point failure mode; unless the pin is required for (say) an external watchdog chip I would recommend disabling the reset pin (requires flash erase) and removing the CR on the pin.

Edit: "but are now stuck in reset across power cycles" - it is possible to have a latch-up condition where a parasitic thyristor-like effect prevents normal operation, typically this can only be removed by a complete removal of power (including full discharge of capacitance on port and supply pins). How long is power removed in the power-cycle mentioned above? Does a 1-minute removal of power make any difference?