RE: SWD interface changing phase from send to receive?

Andrew Lentvorski — Fri, 11 Sep 2015 09:14:42 GMT

Upvoted. Thanks for an actual reference with edges in it. You'd think ARM would put this in their other documentation somewhere.

Yeah, the turnaround looks stupid from an outside point of view, but after thinking about it for a while it makes sense when you consider that that target has no running clock other than what is being provided by the debug probe.

On target receive, the target has to 1) Sample on clock rising edge and then 2) do something with that sample on the clock falling edge. On target transmit, the target has to 1) Prepare something on clock falling edge and then 2) put that something on the line on the clock rising edge.

And that's why the turnaround cycles are where they are. That way the system has an extra clock cycle to do something when it has to.

Sigh. All this effort to avoid using 3 signals (SCK, SDO, SDI) instead of two (SCK, SDO/SDI) when most people would rather have the ability to use a dedicated SWO-like signal anyway.

RE: SWD interface changing phase from send to receive?

RK — Thu, 10 Sep 2015 09:46:14 GMT

Having researched this properly and read the documentation again, I'll move it from comment to answer.

The debug unit is a standard ARM one and all the documentation for it is the standard ARM documentation.

The description of the SWD wire protocol is at infocenter.arm.com/.../DUI0499J_arm_ds5_arm_dstream_reference_guide.pdf section 2.1.2 where it has a useful figure and a table.

The table confirms what you see. Both the probe and the target read data on a rising SWDCLK, however the target writes data on a rising SWDCLK but the probe writes data on a falling SWDCLK.

I didn't instantly see how the probe could read and the target write on a rising CLK, wouldn't the data be changing, however it makes sense when you realise that the probe is generating the clock, and the target is detecting the clock.

So when the probe reads, it does so when the CLK line is low, just before it sets it high, ie just before it generates the rising edge. So as soon as the target detects the rising edge, it can write new data, the probe has already read it, guaranteed. However when the target has data to read it also does it on a rising edge, but it needs to detect the edge, hence the probe has to raise the CLK to high and then leave the data valid for long enough for the target to read it, it gives the target 1/2 a cycle, while the CLK is high and after it puts it back low, then it writes the next bit of data while it's low, then repeats the cycle.

This gives the target one complete cycle to write new data and a 1/2 cycle to detect the clock rising edge and read data.