nRF52840 DK No SPI write hold time

RE: nRF52840 DK No SPI write hold time

Håkon Alseth — Thu, 08 Sep 2022 13:22:11 GMT

Yes, that's correct. A SPI device samples in the middle of a clock period, to ensure that all states are settled.

Kind regards,

Håkon

RE: nRF52840 DK No SPI write hold time

AnomalySmith — Thu, 08 Sep 2022 13:10:32 GMT

Thank you for your reply.
So, if I understand correctly, it's actually not a big deal if the sampling SCLK edge goes along with the bit change as long as "t_SPIM,VMO" is less than a certain period (here 59ns) ?

RE: nRF52840 DK No SPI write hold time

Håkon Alseth — Thu, 08 Sep 2022 10:54:57 GMT

Hi,

[quote user=""]display's IC datasheet says to be >40ns.[/quote]

It states >20 ns for tDHW in the ssd1333 datasheet, while the setup time is specified to 40 ns.

The parameter tSPIM,HMO tells how long it will take for SPIM to react to a future change in the value of MOSI, not a new period start. That is, It takes some time to update the value of MOSI after the clock has changed

If you are afraid of the validity of the signal, you should look at parameter "t_SPIM,VMO" instead, as this gives you the max time of clock edge to MOSI valid.

[quote user=""]I didn't see any configuration option to act on the write hold time yet but I've some warnings about the board and don't know if it may interfere : [/quote]

These are warnings based on duplicate address offset definitions, which can safely be ignored.

Kind regards,

Håkon