nRf52832 CIAA reference layout

RE: nRf52832 CIAA reference layout

Kaja — Mon, 26 Sep 2022 06:03:28 GMT

Great!

Also note: When you have designed a pcb, schematic or/and layout, feel free to upload the designs files to a DevZone case, call it HW review, make it private if you want it to be confidential, and we can give you a design review.

Best regards,
Kaja

RE: nRf52832 CIAA reference layout

Francesco_M — Fri, 23 Sep 2022 13:32:03 GMT

Hi Kaja,

many thanks for your answer. Now I understand. I didn't know the microvia technology and now I learn that this particular vias built with a laser have an aspect ratio of about 1:1 and therefore usually connect only two layers.

RE: nRf52832 CIAA reference layout

Kaja — Fri, 23 Sep 2022 12:44:06 GMT

Hi,

I will try to answer you:

[quote user=""]would like to know why you used a blind via from top layer to inner layer 1 to routing some nets connected to some pins for nRF52832 inside inner 1.[/quote]

We do this to route out all the GPIO's, so that all of them can be used.

[quote user=""]Which are the drawbacks to use these vias from top to bottom and isolate them (obviously) in the inner 2 and bottom layers?[/quote]

If I understand you correctly: This vias goes from top layer to mid-layer 1, because of the size of the via. The size is small, to fit the pad and room we have, and the aspect ratio then sets the restricitons for hole depth.

Best regards,
Kaja