SPI Clock edge too slow

RE: SPI Clock edge too slow

Simonr — Wed, 09 Nov 2022 10:16:10 GMT

Glad to hear that Glenn! That should be fine. Let me know if you have any further follow ups.

Best regards,

Simon

RE: SPI Clock edge too slow

GLNeedham — Tue, 08 Nov 2022 18:52:59 GMT

Simon,

Thanks for your help. We could not get the gpio_pin_configure() to work in the main code, even after spim initialisation. However, we did change the configuration of the clock pin in the low level SPIM source gpio_pin_configure() function in v2.1.0\modules\hal\nordic\nrfx\drivers\src and that had the desired affect.

With the H1H0 drive set the SPIM works fine.

Thanks again

Glenn

RE: SPI Clock edge too slow

Simonr — Tue, 08 Nov 2022 13:25:47 GMT

Hi Glenn

I think this should be the correct way to sett the drive of GPIOs. As ong as you call the gpio_pin_configure after Zephyr has initialized the drivers/libraries used in your project. To make sure that the GPIO config register (PIN-CNF) is set to high drive you can use a debugger to see the setting of this register. Using the nRF Connect Extension in VS code and the debugger available there should be okay for example.

Best regards,

Simon

RE: SPI Clock edge too slow

GLNeedham — Mon, 07 Nov 2022 14:49:09 GMT

Simon,

We are using Zephyr 3.1.99 so the new variants apply.

In our code we have tried doing:

gpio_pin_configure(g_flash_data.gpio_dev, 20, NRF_GPIO_DRIVE_H0H1);

which we took from the page you linked to (nordic-nrf-gpio.h)

Is this correct?

If so they seem to make absolutely no difference to the drive of GPIO 20

As we follow this with a

spi_result = spi_write(spi_dev, spi_cfg_ptr, &tx);

would the spi_cfg_ptr in that call effectively be reconfiguring the port pins back to their default and effectively ignoring our attempts to change them?

We did note the GPIO_DS_ALT flags but they are indicated as 'deprecated' when we try to use those.

Frankly..... it is all a bit confusing!!

If you have a code example of how to change the pin drive strength that would be VERY useful

Thanks for your help

Glenn

RE: SPI Clock edge too slow

GLNeedham — Fri, 04 Nov 2022 08:22:40 GMT

Simon,

Thanks we will take a look at those flags and use them to set the drive strength

Regards

Glenn

RE: SPI Clock edge too slow

Simonr — Fri, 04 Nov 2022 08:01:08 GMT

Hi Glenn

There were some Drive Strength flags in the GPIO peripheral API, but as of Zephyr 3.1.0 the GPIO devicetree flags were refactored, and now the upper 8 bits of gpio_dt_flags_t are now reserved for controller/SoC specific flags. So you should now use the *_GPIO_DS_* specific flags to set drive strength. These are included in nordic-nrf-gpio.h in the Zephyr tree.

Best regards,

Simon

RE: SPI Clock edge too slow

GLNeedham — Thu, 03 Nov 2022 08:28:21 GMT

Simon, Thanks for the reply. We completely undestand the situation with the nrfx driver but my question was specifically about the Zephyr environment.

We cannot find anything in the Zephyr environment which would be an equivilent to configurepins() that allows us to set high drive.

Is it possible in Zephyr to set high drive? and if so how?

Thanks

RE: SPI Clock edge too slow

Simonr — Thu, 03 Nov 2022 08:16:27 GMT

From the nRF52832 product specification (page 523) and nRF91 specification, you can see that the "SPIM clock edge to MOSI valid" timing can indeed be up to 59ns, so if the pins aren't configured to high drive this doesn't seem unlikely. You can use the nrfx driver function configure_pins() in nrfx_spim.c to set SPIM pins to high drive for example.

Best regards,

Simon