RE: Data sheet pin assignment

JONATHAN LL — Tue, 14 Feb 2023 14:29:35 GMT

Adding a update to this.

It is not wrong, its just a bit confusing. Technically the pins are correctly labeled N.C(not connected) as they are not connected to anything internally in the SoC. But in our layout files they are in fact "connected" to the ground layer so that there can be traced traces where the pins are.

So it looks like they are connected to VSS. But they just create the path for traces to connect the center pad to the top layer ground for surrounding area or components.

Regards Jonathan

RE: Data sheet pin assignment

JONATHAN LL — Fri, 16 Dec 2022 21:11:31 GMT

Looks like there is some discrepancies with the table and the schematic for aQFN94

Thanks for reporting will get that clarified.

Use the Schematic and ref design files for reference. You can get the latest reference here https://www.nordicsemi.com/Products/nRF5340/Downloads?lang=en#infotabs

Regards,
Jonathan