Does the SPIS clear its END interrupt when a new transaction starts?

RE: Does the SPIS clear its END interrupt when a new transaction starts?

Stefan Birnir Sverrisson — Mon, 05 Oct 2015 14:13:16 GMT

Any time. I am glad that you figured out the issue

PS. If you do not have enough CPU time for your scenario, nRF52 has an Cortex M4, which is much faster ;)

RE: Does the SPIS clear its END interrupt when a new transaction starts?

Peter Myerscough-Jackopson — Mon, 05 Oct 2015 14:09:09 GMT

It appears it may have simply been a starvation issue, as you suggest. I placed a simple LED toggle function in the spi handler and it toggles infrequently. I am also running in debug mode, so optimisations would not have reduced my code.

Sorry for the noise, and thank you for the help,

Peter

RE: Does the SPIS clear its END interrupt when a new transaction starts?

Stefan Birnir Sverrisson — Mon, 05 Oct 2015 13:51:43 GMT

Hi Peter

The way it is performed in the SPIS driver in the SDK:

The SPI master sets CSN line high which ends the transaction and generates the SPIS->END event
The END_ACQUIRE shortcut is set, making the semaphore to be acquired immediately after the SPIS->END event is received
The SPIS->END event is cleared in SPIS->END interrupt handler
The ACQUIRED event is cleared in the SPIS->ACQUIRED interrupt handler and the buffer operations are performed
Semaphore is released when buffer operations are completed, which will allow the SPIS to send/receive more data

The state machine for the above sequence is shown here.

I have the following understanding of your case, correct me as necessary:

When you receive the high priority interrupt, you manually set the CSN high, which ends the transaction and generates the SPIS->END event
The END_ACQUIRE shortcut is set so the semaphore is requested as soon as the END event is generated by SPIS.
You clear the END event in the END event handler
You do not wait for the ACQUIRED event, but instead read buffer data and release the ACQUIRED event in a high priority interrupt, without knowing if the ACKUIRED event has been received or not.
You end the high priority interrupt with setting CSN low, allowing SPIS to operate if CLK signal is generated with your TIMER
In the ACQUIRED event handler, you release the semaphore again with calling SPIS->RELEASE task, since there are no buffers to relocate.

If this high priority interrupt is generated with high frequency, I suspect that one of the following may happen:

The high frequency interrupt starves the SPIS->END low priority interrupt, because as soon as one high frequency interrupt ends, another one begins. Processing time of the high priority interrupt may take a long time if considerable amount of data has to be copied from the SPIS RX buffer to the FIFO buffer.
The ACQUIRED event handler has not been executed before starting SPIS transmission, therefore the semophore has not been released. In this case all incoming data is ignored by SPIS, and you will probably not receive SPIS->END event when CSN goes high again, since this would not be a valid transaction.
You release the semaphore in your high priority interrupt before it has been acquired, which has no effect. When you set the CSN low again, the semaphore has been acquired by the CPU, so the SPIS can not acquire it, making the SPIS to ignore the following transaction and not generate any SPIS->END event.

The above is just speculation in order to give you ideas of possible failure scenarios. I feel I do not understand your scenario or sequence sufficiently yet do draw any conclusions.

RE: Does the SPIS clear its END interrupt when a new transaction starts?

Peter Myerscough-Jackopson — Mon, 05 Oct 2015 08:16:46 GMT

Stefan,

I am not 'actively' checking/acquiring the interrupt, but...
I do have the END_ACQUIRE shortcut enabled, and in the high priority interrupt handler I am releasing the semaphore.
I am not changing the buffers because I am reusing all the buffer locations. I am performing an SPI read operation that the external device requires a single byte command to start. I am setting the TXDPTR to point to a buffer holding this command, as well as writing the byte to the ORC and DEF registers.

The read data is being copied from the buffer the SPIS points to, into a FIFO, but the pointer in the SPIS is not changed.

Peter

RE: Does the SPIS clear its END interrupt when a new transaction starts?

Stefan Birnir Sverrisson — Fri, 02 Oct 2015 17:30:55 GMT

Hi Peter

Thanks for you question

Where are you acquiring the semaphore? Do you have the END_ACQUIRE shortcut enabled? Are you not waiting for the ACQUIRED event before proceeding with the buffer operation?