4 second current spikes during sleep

RE: 4 second current spikes during sleep

Vidar Berg — Mon, 06 Mar 2023 12:46:58 GMT

Hi Wael,

The EasyDMA current you are seeing comes from the 64 MHz clock and is not really affected by the RAM retention settings. There is not much that can be done about this, other than increasing the VDD voltage with DCDC enabled, unfortunately.

RAM retention has more impact on the System ON idle current as you can see from the PS values here:

The retention current for each 4K RAM section is about 30 nA on average.

[quote user="whazin"]are there any library functions/APIs to do these kind of things?[/quote]

Support for this is currently not integrated in Zephyr as far as I can tell. However, you can use the HAL to access the settings directly: https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/nrfx/drivers/power/hal.html#c.nrf_power_rampower_mask_on.

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Fri, 03 Mar 2023 18:59:50 GMT

Hi Vidar,

I hope all is well with you. I have noticed that one can control the different RAM regions with RAM[n].POWER registers. Can this allow me to save on the EasyDMA current consumption(~2mA) if I was to powerdown some of the RAM regions? if so, how would I go about doing that? are there any library functions/APIs to do these kind of things? As always, your help will be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Mon, 13 Feb 2023 12:09:45 GMT

Hi Wael,

bt_gatt_notify_cb() uses the system work queue to run the callback function. This is why it behaves differently if called from the same work queue context. If it hadn't, it could have become stuck waiting for the resource to be freed.

From the API documentation (link):

A solution may be to queue up 'CONFIG_BT_CONN_TX_MAX' notification packets, then wait for the callbacks to arrive before queueing up more packets again.

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Fri, 10 Feb 2023 21:35:08 GMT

hi Vidar,

Again, thanks for your reply. With regards to the 4k SPIM transfer issue, my receive buffer length was set to 256. dumb mistake on my part. My next task after implementing the the GPIOTE/SPIM/PPI functionality is to upload the FRAM data via BLE to a PC. So I did a little search to see what the best path for uploading data with the maximum throughput and I came across the following link:

Building a Bluetooth application on nRF Connect SDK - Part 3 Optimizing the connection

which is great and what exactly what I'm looking for.

so I grabbed the thread function they implemented their test in and added it to my code. ran as expected. since I don't want to use a thread, I implemented a work item with the same logic. when using the work item, I receive the error " bt_conn: Unable to allocate TX context" because the transmit buffers are getting full. but when using the thread, this does not happen and the thread blocks til new packet space becomes available. The following is from the post:

"In this example, the application sends as quick as possible 300 notification packets in a simple loop. What we noticed from the test was that bt_gatt_notify_cb() will not return -ENOMEM when the buffer is full. Instead, the function that requests the notification buffer will wait with K_FOREVER for the buffer to be available. This is different from the legacy Softdevice. In Softdevice, if we queue the notification and receive NRF_ERROR_RESOURCES (buffer full), we will need to wait for the BLE_GATTS_EVT_HVN_TX_COMPLETE to retry again. In nRF Connect SDK, it's a blocking function instead, and we need to keep the data alive until the function is returned. Note that unlike bare-metal applications (e.g nRF5 SDK) blocking function in RTOS won't keep the CPU in a busy loop."

I can NOT figure out why the same function calls behave differently between the thread and a work item. I also noticed in the work item, the connection parameters are requested but the connection parameter completed isn't completed unless I change the connection parameters by hand on the NRF Connect BLE App. As always, any help would be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Wed, 08 Feb 2023 14:02:50 GMT

Hi Wael,

Sorry for the delayed response. I cannot think of any explanation for why it fails with larger buffers. The 52833 has a 16 bit wide DMA pointer, so it should have no problem with a 4K buffer. Also, it should not make any difference if the SPIM start task was triggered in SW or in HW by the PPI.

Are you able to check to read out the SPIM registers when it hangs? It would be interesting to know what the RXD.MAXCNT and RXD.AMOUNT registers are set to when this happens.

[quote user="whazin"]thank again for your reply. I completely understand what mean by not being able to perform my design requirements without cpu intervention. All I'm trying to say is that because of the spec I mentioned, the assumption I made; since no constraints were given with regards to timing between the PPI/SPIM/CPU, one would assume the functionality I was trying to so is a feasible task. I think the spec needs to be updated to highlight the timing shortcomings I encountered. [/quote]

I agree it may make sense to include a section with best practices when it comes to the use of the PPI. I will report this as a feature request/improvement internally.

[quote user="whazin"]I have already implemented the timing fix last week using a 16us delay and it works as expected. Not sure how to implement a spim callback post a ppi transaction. I would like to see a piece of code to show how to implement that if possible. again, thank you for all your help.[/quote]

PPI is more suitable when you want to perform a repeated transfer. For single transfers such as writing dummy bytes to wake up the fram, or to set the WREN, I think it's better to not use PPI at all.

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Tue, 07 Feb 2023 00:32:32 GMT

hi Vidar,

one last question, why am I not able to receive 4K bytes via the spim 1 bus, NOT using PPI? it seems to hang. when I lower the rx value to something below or equal to 255, it works. your help will be greatly appreciated.

Regards,

RE: 4 second current spikes during sleep

Wael — Mon, 06 Feb 2023 15:16:09 GMT

hi Vidar,

thank again for your reply. I completely understand what mean by not being able to perform my design requirements without cpu intervention. All I'm trying to say is that because of the spec I mentioned, the assumption I made; since no constraints were given with regards to timing between the PPI/SPIM/CPU, one would assume the functionality I was trying to so is a feasible task. I think the spec needs to be updated to highlight the timing shortcomings I encountered.

I have already implemented the timing fix last week using a 16us delay and it works as expected. Not sure how to implement a spim callback post a ppi transaction. I would like to see a piece of code to show how to implement that if possible. again, thank you for all your help.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Fri, 03 Feb 2023 11:18:09 GMT

Hi Wael,

What I meant to say is that our PPI and DMA do not offer the flexibility needed to perform all your SPI transactions in HW without CPU involvement, not that you could have used the PPI differently. Because even with double buffering, you still need the CPU to update the buffer pointers. A task which is not synchronized to your TIMER/PPI processes running in the background.

The EasyDMA array list feature coupled with a TIMER and PPI works great when you want to perform repeated SPI transfers in the background (each array element must be of the same size). For instance, when sampling a high-speed ADC or refreshing a display. PPI has many other uses too. Often it is used to trigger a task with consistent timing (e.g. for bit banging a serial protocol). It can also be useful for reducing the number of interrupts in CPU bound applications.

[quote user="whazin"]How else do you suggest to use the CPU more? [/quote]

You could for instance enable the SPIM callback and schedule subsequent transfers from there, but this would require major changes to your design, which I can understand is not desirable at this point.

As a workaround, maybe you can add a delay between step 4) and 5) like the one you had on step 3? Alternatively, try to change the WREN transaction as I suggested in my previous reply.

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Thu, 02 Feb 2023 20:23:15 GMT

hi Vidar,

I'm not sure I fully understand by what you mean when you say:

"It will not be possible to completely offload the CPU with PPI/DMA in this case because the transfers have varying lengths. "

This is from the 52833 product spec....

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next transmission immediately after having received the STARTED event.

https://infocenter.nordicsemi.com/index.jsp?topic=%2Fdrivers_nrfx_v2.8.0%2Fgroup__nrfx__gpiote.html

This is exactly what I'm doing!

How else am I suppose to update these pointers aside from an ISR? is there any other way?

what am I missing and what is the point of the PPI if this can't be done?

How else do you suggest to use the CPU more?

I agree with your edit and will update that.

I really appreciate your help and not trying to sound upset but I am a little frustrated. I need to put this issue behind me and any help will be greatly appreciated.

Thanks again,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Thu, 02 Feb 2023 19:57:27 GMT

Hi Wael,

The problem as I see it is that you need to rely on the timer ISR to set up your transfers. Whether the timer ISR will be serviced in time depends on the interrupt latency, if the IRQ becomes blocked by other interrupts in the system, and the time it takes to complete a current ongoing SPI transfer.

It will not be possible to completely offload the CPU with PPI/DMA in this case because the transfers have varying lengths. While I can understand why you want to leverage the PPI to optimize performance, I do think this implementation would have benefited by using the CPU more. This would have made it easier to control the transfer sequences and reduced the overall complexity. I am not sure if the PPI will lead to any noticeable power savings either considering how "cheap" CPU processing has become.

[quote user="whazin"]I also tried your suggestion to to do a FRAM read which requires 4 bytes(1 byte command, 3 byte address), I see what I would expect from this timing issue,[/quote]

Sorry, what I meant to suggest was that you changed your WREN transaction to include 10 RX bytes. I am not sure if your FRAM IC will like this, but it should increase the transfer time, at least.

void fram_spim_start_count_ppi_timer_event_handler(nrf_timer_event_t event_type, void * p_context)
{
    uint32_t timer_value = 0;
    uint8_t CMD_WRITE_ENABLE;
    uint8_t CMD_HIBERNATE;
    uint32_t dummy[10];

    if(event_type == NRF_TIMER_EVENT_COMPARE0) // for 2nd fram write
    {
        timer_value = nrfx_timer_capture_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL0);
        CMD_WRITE_ENABLE = ENUM_TO_UINT8(FRAM_CMD_WRITE_ENABLE);
        spim1_fram.p_reg->TXD.PTR = (uint32_t)&CMD_WRITE_ENABLE;
        spim1_fram.p_reg->RXD.PTR = &dummy;
        spim1_fram.p_reg->TXD.MAXCNT = 1;
        spim1_fram.p_reg->RXD.MAXCNT = 10; 
       // LOG_INF("Setup for 2nd fram write.........");

        //nrfx_timer_clear(&m_imu_acq_cnt_timer);
        // LOG_HEXDUMP_INF(IMU_Recv_ArrayList->buffer,364,"received FIFO Data");
    }
    else if(event_type == NRF_TIMER_EVENT_COMPARE1) // for 3rd fram write
    ...

Regards,

Vidar

Edit: forgot to add that you should consider placing the CMD_WRITE_ENABLE and CMD_HIBERNATE variable in static memory. Otherwise, there is a risk that they can become overwritten by another interrupt before the SPI has transferred the command. The same goes for my dummy array, except the consequences may be worse as it can potentially lead to stack corruption.

RE: 4 second current spikes during sleep

Wael — Thu, 02 Feb 2023 18:59:27 GMT

hi Vidar,

thanks for your reply. The issue is exactly as you describe and what I tried to do also, lol.

"race where PPI is triggering the FRAM SPI start task before the CPU has had time to update the transaction details from your timer ISR. Thus, causing the WREN byte to be sent twice instead of proceeding with IMU data transfer as it is supposed to."

And that is what I am seeing on the oscilloscope. when I have the 2nd SPIM transaction configured for 10 bytes with 8 MHz speed, I see the following which is what I expect to see:

3500 byte transfer from IMU -> 4 byte transfer to FRAM -> 8ms time delay -> 10 byte transfer to FRAM -> 3500 byte transfer to FRAM -> 1 byte transfer to FRAM

if I change the "10 byte transfer to FRAM" to anything less than 10, say X, I would see the following:

3500 byte transfer from IMU -> 4 byte transfer to FRAM -> 8ms time delay -> X byte transfer to FRAM -> X byte transfer to FRAM -> X byte transfer to FRAM

the only way to get the "X" number to be 1 as I need is to have the FRAM SPIM bus configured to 1 MHz.

so clearly the timer ISR to update the transaction details is not getting triggered. This is also happening on subsequent transactions.

I also tried your suggestion to to do a FRAM read which requires 4 bytes(1 byte command, 3 byte address), I see what I would expect from this timing issue,

3500 byte transfer from IMU -> 4 byte transfer to FRAM -> 8ms time delay -> 4 byte transfer to FRAM -> 4 byte transfer to FRAM -> 4 byte transfer to FRAM

so my conclusion is that the PPI/SPIM mechanism for multiple transaction is not functioning as intended because of the race condition I am seeing. Therefore, I really need some workaround to get me by. Can you please check internally maybe with the design team to try to get to the bottom of this. can this have something to do with the errata issue?

Even using the 1MHz SPIM speed leaves me extremely uncomfortable as I do not know if more logic added to my application may increase the likelihood of the race condition.

as always, your help will be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Thu, 02 Feb 2023 15:01:12 GMT

Hi Wael,

I am happy to hear you found the errata which caused the issue. This errata is quite rare and is usually more intermittent due to the accurate timing conditions needed for it to arise.

[quote user="whazin"]Just confirmed my feeling from my previous post where the time to write one byte(step 4 only from previous post) was creating a timing issue. when I changed that to 10 bytes and the FRAM SPIM freq to 8MHz, it worked. anything under 10 bytes will not. [/quote]

I wonder if the problem could be caused by a race where PPI is triggering the FRAM SPI start task before the CPU has had time to update the transaction details from your timer ISR. Thus, causing the WREN byte to be sent twice instead of proceeding with IMU data transfer as it is supposed to. Or does this not match with what you are seeing on the oscilloscope?

As a test, maybe you can read out 10 dummy bytes in the WREN transaction to see if it has the same effect as sending 10 bytes.

Best regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Thu, 02 Feb 2023 00:49:43 GMT

Hi Vidar,

Just confirmed my feeling from my previous post where the time to write one byte(step 4 only from previous post) was creating a timing issue. when I changed that to 10 bytes and the FRAM SPIM freq to 8MHz, it worked. anything under 10 bytes will not. Not sure how I'm suppose to handle this issue. I need to only write one byte, which is a command, and the CS line needs to be toggled. Your help will be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Wael — Thu, 02 Feb 2023 00:16:39 GMT

hi Vidar,

thanks for the reply. I did try TIMER SHUTDOWN and that did not work. what did work was the following:

// nRF52833 Revision 2 Errata

// [246] System: Intermittent extra current consumption when going to sleep

// Extra current consumption in the range of 350 µA when in System On Idle.

// A high-speed peripheral (CPU for example) accesses a RAM block which is being accessed by

// a low-speed peripheral through the DMA bus, with a specific timing, and the high-speed peripheral has

// higher priority than the low-speed peripheral.

// NOTE: Workaround consequences: Up to 40 µA current increase when the 16 MHz clock is used.

*(volatile uint32_t *)0x4007AC84ul = 0x00000002ul;

I placed that line of code in my main function and the current went back down close to what's expected. still need to figure out where about 20uA is going.

having said that, I now have the issue where if I increase my FRAM SPIM frequency to anything above 1 MHz, the PPI logic does not work. IMU SPIM frequency is set to 8 MHz. recall that the IMU and FRAM are on separate buses. recall, my app does the following using PPI

the PPI configuration is as follow:

1) Upon receiving a GPIOTE trigger from an IMU(every 8.3 seconds), read its data (this is operating on a dedicated spi bus, SPIM0) (~3500 bytes)

2) write a dummy read command to an FRAM IC to wake it up from hibernate state (SPIM1 bus)(4 bytes)

3) trigger timer for 8ms from the start of the FRAM SPIM transaction(step 2)(8ms is the period for FRAM to become stable from hibernate state)

4) write the WREN(write enable) command(1 Byte) to the FRAM upon completion of the 8ms timer

5) write the (write command, address, data) to the FRAM(~3500 bytes)

6) write the hibernate command to the FRAM(1 byte)

so when the FRAM SPIM freq=1 MHz, everything looks good and I can see things operating as expected on a scope.

when I change the freq. to say 2 MHz or more, it does everything as expected with the exception of step 5. it only writes ONE byte. its seems as though the fram_spim_start_count_ppi_timer_event_handler is not getting executed on when the count=2(to setup for the 3rd FRAM write) to update the SPIM ptr and tx/rx parameters. I am assuming the 2nd spi transaction(which is one byte) got executed so fast that the spi parameters never get updated for the next transaction. Not sure on how to handle this issue. I need the speed to save on power. any thoughts and/or hints? As always, your help would be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Wed, 01 Feb 2023 12:50:23 GMT

Hi Wael,

Sorry, I thought you were using the nRF5340 for some reason. A current draw in the 5-600 uA range on the nRF52 series usually indicates that a peripheral keep requesting the 16 MHz clock. For instance, a running TIMER instance. However, this should have led to a more constant draw, not like the waveform shown in your screenshot.

The DMA current is closer to 2 mA with VDD @ 1.8 v. But as you said, this current should only be seen during transmissions when the CPU is idle.

Either way, to try narrow down the problem, could try to issue the TIMER SHUTDOWN tasks for your timers after the transaction is complete by calling nrfx_timer_disable(). Also, is it possible to power off the IMU and FRAM IC (make sure you do not have any floating inputs if you do this)?

Best regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Tue, 31 Jan 2023 22:26:03 GMT

Hi Vidar,

Thank you for your suggestion, but I am not using the 5340 which is what your link, I am using 52833 and SDK 2.0.0.

with that said, here is my function that initializes the GPIOTE pin

void configure_imu_int1_gpiote(void)
{
    nrfx_err_t err = NRFX_SUCCESS;

     __ASSERT (!nrfx_gpiote_is_init(),"nrfx_gpiote_is_init Failed");
    
    static const nrfx_gpiote_input_config_t input_config = {
		.pull = NRF_GPIO_PIN_PULLDOWN,
	};

	const nrfx_gpiote_trigger_config_t trigger_config = {
		.trigger = NRFX_GPIOTE_TRIGGER_LOTOHI,
		.p_in_channel = NULL, //&in_channel,
	};

    err = nrfx_gpiote_input_configure(IMU_INT1_PIN,
					  &input_config,
					  &trigger_config,
					  NULL);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("Failed to nrfx_gpiote_input_configure, error: 0x%08X", err);
		return;
	}

    //nrfx_gpiote_in_event_enable(IMU_INT1_PIN, false);
    nrfx_gpiote_trigger_enable(IMU_INT1_PIN, false);
}

I am NOT using IN Event per my configuration. Please note this power issue only happens after all configurations and ONLY after the IMU int pin is triggered. so after power on for approx 8 seconds, the current level is as expected. only after the int trigger this issue happens. again, this issue is driving me crazy and eating lots of my time. any other suggestions please? as always, your help is greatly appreciated.

Regards,

here is some of my code

timers setup

static const nrfx_timer_t m_imu_acq_cnt_timer = NRFX_TIMER_INSTANCE(1);
static const nrfx_timer_t m_fram_hibernate_delay_timer = NRFX_TIMER_INSTANCE(2);
static const nrfx_timer_t m_fram_spim_start_cnt_timer = NRFX_TIMER_INSTANCE(3);
static const nrfx_timer_t m_fram_spim_end_cnt_timer = NRFX_TIMER_INSTANCE(4);


void configure_imu_ppi_timer(void)
{
    nrfx_err_t err = NRFX_SUCCESS;


    // configure imu/ppi timer
    nrfx_timer_config_t timer_cfg_0 = NRFX_TIMER_DEFAULT_CONFIG;
    timer_cfg_0.mode = NRF_TIMER_MODE_LOW_POWER_COUNTER; //NRF_TIMER_MODE_COUNTER;
    //IRQ_DIRECT_CONNECT(TIMER1_IRQn, 0, nrfx_timer_1_irq_handler, 0);

    IRQ_CONNECT(DT_IRQN(DT_NODELABEL(timer1)), 
		    DT_IRQ(DT_NODELABEL(timer1), priority),
		    nrfx_isr, nrfx_timer_1_irq_handler, 0);

    if(!nrfx_timer_is_enabled(&m_imu_acq_cnt_timer)) {
        err = nrfx_timer_init(&m_imu_acq_cnt_timer,
                                    &timer_cfg_0,
                                    imu_ppi_timer_event_handler);    
        if (err != NRFX_SUCCESS) {
		    LOG_ERR("nrf_drv_timer_init error: %08x", err);
		    return;
	    }                              
    }

    nrfx_timer_extended_compare(&m_imu_acq_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL0,
                                   1 /*IMU_SPIM_TRANSFER_COUNT*/,
                                   NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK, 
                                   true);

    if(!nrfx_timer_is_enabled(&m_imu_acq_cnt_timer))
        nrfx_timer_enable(&m_imu_acq_cnt_timer);    
}

void configure_fram_ppi_timer()
{
    nrfx_err_t err = NRFX_SUCCESS;

    IRQ_CONNECT(DT_IRQN(DT_NODELABEL(timer2)), 
		    DT_IRQ(DT_NODELABEL(timer2), priority),
		    nrfx_isr, nrfx_timer_2_irq_handler, 0);

    // the fram hibernate timer ~6ms
    nrfx_timer_config_t timer_cfg_1 = NRFX_TIMER_DEFAULT_CONFIG;
    timer_cfg_1.mode = NRF_TIMER_MODE_TIMER;
    timer_cfg_1.frequency = NRF_TIMER_FREQ_31250Hz;
    //timer_cfg_1.bit_width = NRF_TIMER_BIT_WIDTH_32;

    if(!nrfx_timer_is_enabled(&m_fram_hibernate_delay_timer)) {
        err = nrfx_timer_init(&m_fram_hibernate_delay_timer,
                                    &timer_cfg_1,
                                    fram_ppi_timer_event_handler);    
        if (err != NRFX_SUCCESS) {
		    LOG_ERR("nrf_drv_timer_init error: %08x", err);
		    return;
	    }                              
    }
    uint32_t ticks = nrfx_timer_ms_to_ticks(&m_fram_hibernate_delay_timer, 8);
    nrfx_timer_extended_compare(&m_fram_hibernate_delay_timer,
                                   NRF_TIMER_CC_CHANNEL2,
                                   ticks,
                                   (NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK | NRF_TIMER_SHORT_COMPARE2_STOP_MASK), 
                                   false);    

    nrfx_timer_clear(&m_fram_hibernate_delay_timer);
    //  if(!nrfx_timer_is_enabled(&m_fram_hibernate_delay_timer))
    //  {
    //     nrfx_timer_enable(&m_fram_hibernate_delay_timer);
    //     nrfx_timer_pause(&m_fram_hibernate_delay_timer);
    //     nrfx_timer_clear(&m_fram_hibernate_delay_timer);
    //  }

    IRQ_CONNECT(DT_IRQN(DT_NODELABEL(timer3)), 
		    DT_IRQ(DT_NODELABEL(timer3), priority),
		    nrfx_isr, nrfx_timer_3_irq_handler, 0);

    // configure fram spim start count ppi timer
    nrfx_timer_config_t timer_cfg_2 = NRFX_TIMER_DEFAULT_CONFIG;
    timer_cfg_2.mode = NRF_TIMER_MODE_LOW_POWER_COUNTER; //NRF_TIMER_MODE_COUNTER;
    if(!nrfx_timer_is_enabled(&m_fram_spim_start_cnt_timer)) {
        err = nrfx_timer_init(&m_fram_spim_start_cnt_timer,
                                    &timer_cfg_2,
                                    fram_spim_start_count_ppi_timer_event_handler);    
        if (err != NRFX_SUCCESS) {
		    LOG_ERR("nrf_drv_timer_init error: %08x", err);
		    return;
	    }                              
    }
    nrfx_timer_compare(&m_fram_spim_start_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL0,
                                   1 /*FRAM_SPIM_TRANSFER_COUNT*/, 
                                   true);

    nrfx_timer_compare(&m_fram_spim_start_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL1,
                                   2 /*FRAM_SPIM_TRANSFER_COUNT*/, 
                                   true);

    nrfx_timer_compare(&m_fram_spim_start_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL2,
                                   3 /*FRAM_SPIM_TRANSFER_COUNT*/, 
                                   true);
    nrfx_timer_extended_compare(&m_fram_spim_start_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL3,
                                   4 /*FRAM_SPIM_TRANSFER_COUNT*/, 
                                   NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK,
                                   true);                               

    if(!nrfx_timer_is_enabled(&m_fram_spim_start_cnt_timer))
        nrfx_timer_enable(&m_fram_spim_start_cnt_timer);  

    nrfx_timer_clear(&m_fram_spim_start_cnt_timer);

    IRQ_CONNECT(DT_IRQN(DT_NODELABEL(timer4)), 
		    DT_IRQ(DT_NODELABEL(timer4), priority),
		    nrfx_isr, nrfx_timer_4_irq_handler, 0);

    // configure fram spim end count ppi timer
    nrfx_timer_config_t timer_cfg_3 = NRFX_TIMER_DEFAULT_CONFIG;
    timer_cfg_3.mode = NRF_TIMER_MODE_LOW_POWER_COUNTER; //NRF_TIMER_MODE_COUNTER;
    if(!nrfx_timer_is_enabled(&m_fram_spim_end_cnt_timer)) {
        err = nrfx_timer_init(&m_fram_spim_end_cnt_timer,
                                    &timer_cfg_3,
                                    fram_spim_end_count_ppi_timer_event_handler);    
        if (err != NRFX_SUCCESS) {
		    LOG_ERR("nrf_drv_timer_init error: %08x", err);
		    return;
	    }                              
    }
    // we start the 3rd FRAM write
    nrfx_timer_compare(&m_fram_spim_end_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL0,
                                   2 /*SPIM END EVENT COUNT*/,  
                                   false);
    // we start the 4th FRAM write
    nrfx_timer_compare(&m_fram_spim_end_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL1,
                                   3 /*SPIM END EVENT COUNT*/,
                                   false);
    // we want to clear the timer on the end of the 4th spim end 
     nrfx_timer_extended_compare(&m_fram_spim_end_cnt_timer,
                                   NRF_TIMER_CC_CHANNEL2,
                                   4 /*SPIM END EVENT COUNT*/,
                                   NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK,  
                                   false);
                             
    if(!nrfx_timer_is_enabled(&m_fram_spim_end_cnt_timer))
        nrfx_timer_enable(&m_fram_spim_end_cnt_timer);     

    nrfx_timer_clear(&m_fram_spim_end_cnt_timer); 

}

void fram_spim_start_count_ppi_timer_event_handler(nrf_timer_event_t event_type, void * p_context)
{
    uint32_t timer_value = 0;
    uint8_t CMD_WRITE_ENABLE;
    uint8_t CMD_HIBERNATE;

    if(event_type == NRF_TIMER_EVENT_COMPARE0) // for 2nd fram write
    {
        timer_value = nrfx_timer_capture_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL0);
        CMD_WRITE_ENABLE = ENUM_TO_UINT8(FRAM_CMD_WRITE_ENABLE);
        spim1_fram.p_reg->TXD.PTR = (uint32_t)&CMD_WRITE_ENABLE;
        spim1_fram.p_reg->TXD.MAXCNT = 1;
        spim1_fram.p_reg->RXD.MAXCNT = 0; 
       // LOG_INF("Setup for 2nd fram write.........");

        //nrfx_timer_clear(&m_imu_acq_cnt_timer);
        // LOG_HEXDUMP_INF(IMU_Recv_ArrayList->buffer,364,"received FIFO Data");
    }
    else if(event_type == NRF_TIMER_EVENT_COMPARE1) // for 3rd fram write
    {
        timer_value = nrfx_timer_capture_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL1);
        IMU_RX_BUFFER[0] = ENUM_TO_UINT8(FRAM_CMD_WRITE_DATA);
        IMU_RX_BUFFER[1] = (m_current_fram_addr & 0x00FF0000) >> 16;
        IMU_RX_BUFFER[2] = (m_current_fram_addr & 0x0000FF00) >> 8;
        IMU_RX_BUFFER[3] = (m_current_fram_addr & 0x000000FF);

        m_current_fram_addr += ADL_MODE_BUFFER_IMU_RXD_SIZE;

        spim1_fram.p_reg->TXD.PTR = (uint32_t)&IMU_RX_BUFFER;
        spim1_fram.p_reg->TXD.MAXCNT = ADL_MODE_BUFFER_IMU_RXD_SIZE + 4;
        spim1_fram.p_reg->RXD.MAXCNT = 0;
       // LOG_INF("Setup for 3rd fram write.........");
    }
    else if(event_type == NRF_TIMER_EVENT_COMPARE2) // for 4th fram write
    {
        timer_value = nrfx_timer_capture_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL2);
        CMD_HIBERNATE = ENUM_TO_UINT8(FRAM_CMD_HIBERNATE);
        spim1_fram.p_reg->TXD.PTR = (uint32_t)&CMD_HIBERNATE;
        spim1_fram.p_reg->TXD.MAXCNT = 1;
        spim1_fram.p_reg->RXD.MAXCNT = 0; 
       // LOG_INF("Setup for 4th fram write.........");
    }
    else if(event_type == NRF_TIMER_EVENT_COMPARE3) // for 1st fram write
    {
        timer_value = nrfx_timer_capture_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL3);
      //  nrfx_timer_clear(&m_fram_spim_start_cnt_timer);
        spim1_fram.p_reg->TXD.PTR = (uint32_t)&FRAM_ADL_TX_ArrayList;
        spim1_fram.p_reg->TXD.MAXCNT = 4;
        spim1_fram.p_reg->RXD.MAXCNT = 0; 
        //LOG_INF("Setup for 1st fram write.........");
    }
    else
        LOG_INF("Unknown timer event...............");
}
void fram_spim_end_count_ppi_timer_event_handler(nrf_timer_event_t event_type, void * p_context)
{
    if(event_type == NRF_TIMER_EVENT_COMPARE0) // the 3rd spim end trigger
    {
        LOG_INF("2nd spim end trigger.........");
    }
    else if(event_type == NRF_TIMER_EVENT_COMPARE1) // the 3rd spim end trigger
    {
        //nrfx_timer_clear(&m_fram_spim_end_cnt_timer);
        LOG_INF("3rd spim end trigger.........");
    }
    else
        LOG_INF("Undefind FRAM SPIM End Count Event Type.........");
}

void setup_ADL_mode_imu_ppi_spi_transfer(void)
{
    nrfx_err_t err = NRFX_SUCCESS;
  
    // IMU SPI setup
    spim0_imu.p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList;
    spim0_imu.p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList;
    spim0_imu.p_reg->TXD.MAXCNT = ADL_MODE_BUFFER_IMU_TXD_SIZE;
    spim0_imu.p_reg->RXD.MAXCNT = ADL_MODE_BUFFER_IMU_RXD_SIZE; 
    nrfx_spim_xfer_desc_t imu_xfer = NRFX_SPIM_XFER_TRX((uint8_t*)IMU_ChannelSwitch_ArrayList,
                                                                        ADL_MODE_BUFFER_IMU_TXD_SIZE,
                                                                        (uint8_t*)&IMU_RX_BUFFER[4],
                                                                        ADL_MODE_BUFFER_IMU_RXD_SIZE);

    uint32_t flags = (NRFX_SPIM_FLAG_HOLD_XFER
                      |NRFX_SPIM_FLAG_TX_POSTINC
                      |NRFX_SPIM_FLAG_RX_POSTINC
                      |NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER
                      |NRFX_SPIM_FLAG_REPEATED_XFER);
                      
    err = nrfx_spim_xfer(&spim0_imu, &imu_xfer, flags);
    if (err != NRFX_SUCCESS) {
        LOG_INF("nrfx_spim_xfer error: %08x", err);
		LOG_ERR("nrfx_spim_xfer error: %08x", err);
		return;
	}
}

void setup_ADL_mode_fram_ppi_spi_transfer(void)
{
    nrfx_err_t err = NRFX_SUCCESS;
  
    uint32_t flags = (NRFX_SPIM_FLAG_HOLD_XFER
                      |NRFX_SPIM_FLAG_TX_POSTINC
                      |NRFX_SPIM_FLAG_RX_POSTINC
                      |NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER
                      |NRFX_SPIM_FLAG_REPEATED_XFER);
                      
    // FRAM SPI setup
    spim1_fram.p_reg->TXD.LIST = SPIM_TXD_LIST_LIST_ArrayList;
    spim1_fram.p_reg->RXD.LIST = SPIM_RXD_LIST_LIST_ArrayList;
    spim1_fram.p_reg->TXD.MAXCNT = 4;
    spim1_fram.p_reg->RXD.MAXCNT = 0; 
    nrfx_spim_xfer_desc_t fram_xfer = NRFX_SPIM_XFER_TRX((uint8_t*)FRAM_ADL_TX_ArrayList,
                                                                        4,
                                                                        NULL,
                                                                        0);                  
    err = nrfx_spim_xfer(&spim1_fram, &fram_xfer, flags);
    if (err != NRFX_SUCCESS) {
        LOG_INF("nrfx_spim_xfer error: %08x", err);
		LOG_ERR("nrfx_spim_xfer error: %08x", err);
		return;
	}
}

void start_ADL_mode_acq()
{
    //setup_imu_ppi_spi_transfer();
    setup_ADL_mode_imu_ppi_spi_transfer();
    setup_ADL_mode_fram_ppi_spi_transfer();
	nrfx_ppi_group_enable(imu_trigger_group);
    
    // k_timer_stop(&m_start_imu_conv_timer_id);
    // k_timer_start(&m_start_imu_conv_timer_id, K_MSEC(1010), K_NO_WAIT);
    LOG_INF("started ADL Mode Acquisition...............");
}

void ADL_mode_ppi_init(void)
{
    nrfx_err_t err = NRFX_SUCCESS;

    nrf_ppi_channel_t imu_int1_trigger_ppi_channel;
    nrf_ppi_channel_t imu_count_ppi_channel;
    nrf_ppi_channel_t imu_trigger_disable_channel;
    nrf_ppi_channel_t fram_spim_end_trigger_ppi_channel;
    nrf_ppi_channel_t fram_spim_start_trigger_ppi_channel;
    nrf_ppi_channel_t fram_hibernate_timer_ppi_channel;
    nrf_ppi_channel_t fram_spim_start_count_ppi_channel;
    nrf_ppi_channel_t fram_spim_end_count_ppi_channel;

    nrf_ppi_channel_t fram_1st_write_ppi_channel;
    nrf_ppi_channel_t fram_2nd_write_ppi_channel;
    nrf_ppi_channel_t fram_3rd_write_ppi_channel;
    nrf_ppi_channel_t fram_4th_write_ppi_channel;

    uint32_t imu_int1_trigger_pin_evt_addr;
    uint32_t imu_spim_start_task_addr;
    uint32_t imu_spim_end_evt_addr;
    uint32_t timer_count_task_addr;
    uint32_t timer_cc_event_addr;
    uint32_t group_imu_disable_task_addr;
    
    uint32_t imu_ss_pin_toggle_task_addr;
    uint32_t fram_timer_spim_start_count_task_addr;
    uint32_t fram_timer_spim_end_count_task_addr;
    uint32_t fram_timer_spim_start_cc1_event_addr;
    uint32_t fram_timer_spim_end_cc2_event_addr;
    uint32_t fram_timer_spim_end_cc3_event_addr;
   
    uint32_t fram_spim_start_task_addr;
    uint32_t fram_spim_end_evt_addr;
    uint32_t fram_spim_started_evt_addr;
    uint32_t fram_ss_pin_toggle_task_addr;
    // uint32_t group_fram_disable_task_addr;

    uint32_t fram_hibernate_timer_start_task_addr;
    uint32_t fram_hibernate_timer_cc_evt_addr;   

    err = nrfx_ppi_channel_alloc(&imu_int1_trigger_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}

    // this ppi channel will toggle the fram spim cs at the end of the transaction to the fram
    err = nrfx_ppi_channel_alloc(&fram_spim_end_trigger_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    
    err = nrfx_ppi_channel_alloc(&fram_spim_start_trigger_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    
    err = nrfx_ppi_channel_alloc(&fram_hibernate_timer_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&imu_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}  
    err = nrfx_ppi_channel_alloc(&fram_spim_start_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&fram_spim_end_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&fram_1st_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&fram_2nd_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&fram_3rd_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&fram_4th_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_alloc(&imu_trigger_disable_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_alloc error: %08x", err);
		return;
	}

    err = nrfx_ppi_group_alloc(&imu_trigger_group);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_group_alloc error: %08x", err);
		return;
	}

    imu_int1_trigger_pin_evt_addr   = nrfx_gpiote_in_event_addr_get(IMU_INT1_PIN);
    imu_spim_start_task_addr        = nrf_spim_task_address_get(spim0_imu.p_reg, NRF_SPIM_TASK_START);
    imu_spim_end_evt_addr           = nrf_spim_event_address_get(spim0_imu.p_reg, NRF_SPIM_EVENT_END);
    timer_count_task_addr       = nrfx_timer_task_address_get(&m_imu_acq_cnt_timer, NRF_TIMER_TASK_COUNT);
    timer_cc_event_addr         = nrfx_timer_compare_event_address_get(&m_imu_acq_cnt_timer, NRF_TIMER_CC_CHANNEL0);
    // group_disable_task_addr = (uint32_t) nrf_ppi_task_group_disable_address_get(trigger_group);
    group_imu_disable_task_addr = (uint32_t) nrfx_ppi_task_addr_group_disable_get(imu_trigger_group);
    
    fram_spim_start_task_addr    = nrf_spim_task_address_get(spim1_fram.p_reg, NRF_SPIM_TASK_START); 
    fram_spim_end_evt_addr       = nrf_spim_event_address_get(spim1_fram.p_reg, NRF_SPIM_EVENT_END);
    fram_spim_started_evt_addr   = nrf_spim_event_address_get(spim1_fram.p_reg, NRF_SPIM_EVENT_STARTED);
 //   group_fram_disable_task_addr = (uint32_t) nrfx_ppi_task_addr_group_disable_get(fram_trigger_group);
    
    fram_hibernate_timer_start_task_addr = nrfx_timer_task_address_get(&m_fram_hibernate_delay_timer, NRF_TIMER_TASK_START);
    fram_hibernate_timer_cc_evt_addr     = nrfx_timer_compare_event_address_get(&m_fram_hibernate_delay_timer, NRF_TIMER_CC_CHANNEL2);

    fram_timer_spim_start_count_task_addr = nrfx_timer_task_address_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_TASK_COUNT);
    fram_timer_spim_end_count_task_addr = nrfx_timer_task_address_get(&m_fram_spim_end_cnt_timer, NRF_TIMER_TASK_COUNT);

    //fram_timer_spim_start_cc1_event_addr         = nrfx_timer_compare_event_address_get(&m_fram_spim_start_cnt_timer, NRF_TIMER_CC_CHANNEL0);
    fram_timer_spim_end_cc2_event_addr         = nrfx_timer_compare_event_address_get(&m_fram_spim_end_cnt_timer, NRF_TIMER_CC_CHANNEL0);
    fram_timer_spim_end_cc3_event_addr         = nrfx_timer_compare_event_address_get(&m_fram_spim_end_cnt_timer, NRF_TIMER_CC_CHANNEL1);

    // IMU SS
    // The SS pin will be driven by a GPIOTE task.
    // have the ppi spim start/end event control the slave select       
    nrfx_gpiote_out_config_t imu_ss_pin_config = NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(true);
    err = nrfx_gpiote_out_init(IMU_CS_PIN, &imu_ss_pin_config);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_gpiote_out_init error: %08x", err);
		return;
	}
    imu_ss_pin_toggle_task_addr = nrfx_gpiote_out_task_addr_get(IMU_CS_PIN);

    // FRAM SS
    // The SS pin will be driven by a GPIOTE task.
    // have the ppi spim start/end event control the slave select   
    nrfx_gpiote_out_config_t fram_ss_pin_config = NRFX_GPIOTE_CONFIG_OUT_TASK_TOGGLE(true);
    err = nrfx_gpiote_out_init(FRAM_CS_PIN, &fram_ss_pin_config);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_gpiote_out_init error: %08x", err);
		return;
	}
    fram_ss_pin_toggle_task_addr = nrfx_gpiote_out_task_addr_get(FRAM_CS_PIN);

    // this channel will trigger the imu spim task off the imu int1 pin event 
    err = nrfx_ppi_channel_assign(imu_int1_trigger_ppi_channel,
                                          imu_int1_trigger_pin_evt_addr,
                                          imu_spim_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}

    // fork the imu ss pin off of the start(to assert) of imu spim channel
    err = nrfx_ppi_channel_fork_assign(imu_int1_trigger_ppi_channel, imu_ss_pin_toggle_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_fork_assign error: %08x", err);
		return;
	}

    err = nrfx_ppi_channel_assign(imu_count_ppi_channel,
                                          imu_spim_end_evt_addr,
                                          timer_count_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    // fork the imu ss pin off of the end of imu spim channel(to de-assert))
    err = nrfx_ppi_channel_fork_assign(imu_count_ppi_channel, imu_ss_pin_toggle_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_fork_assign error: %08x", err);
		return;
	}
 ////////   
    // first FRAM write. dummy read instruction. toggle ss pin, start spi, toggle ss pin  
    err = nrfx_ppi_channel_assign(fram_1st_write_ppi_channel,
                                          imu_spim_end_evt_addr,
                                          fram_spim_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_assign(fram_spim_start_trigger_ppi_channel,
                                          fram_spim_started_evt_addr,
                                          fram_ss_pin_toggle_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_assign(fram_spim_end_trigger_ppi_channel,
                                          fram_spim_end_evt_addr,
                                          fram_ss_pin_toggle_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    
    // count the FRAM SPI writes off of the SPI start
    err = nrfx_ppi_channel_assign(fram_spim_start_count_ppi_channel,
                                          fram_spim_started_evt_addr,
                                          fram_timer_spim_start_count_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	} 
    err = nrfx_ppi_channel_assign(fram_spim_end_count_ppi_channel,
                                          fram_spim_end_evt_addr,
                                          fram_timer_spim_end_count_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
   
    // start the FRAM hibernate timer off of the IMU SPI end Event
    err = nrfx_ppi_channel_assign(fram_hibernate_timer_ppi_channel,
                                          imu_spim_end_evt_addr,
                                          fram_hibernate_timer_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    // now we want to start the 2nd, 3rd and 4th FRAM SPI transactions
    // we start the 2nd off of the end of te hibernate timer
    err = nrfx_ppi_channel_assign(fram_2nd_write_ppi_channel,
                                          fram_hibernate_timer_cc_evt_addr,
                                          fram_spim_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_assign(fram_3rd_write_ppi_channel,
                                          fram_timer_spim_end_cc2_event_addr,
                                          fram_spim_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_assign(fram_4th_write_ppi_channel,
                                          fram_timer_spim_end_cc3_event_addr,
                                          fram_spim_start_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}

    err = nrfx_ppi_channel_enable(fram_spim_start_trigger_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_spim_end_trigger_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(imu_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_spim_start_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_spim_end_count_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_1st_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_2nd_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    err = nrfx_ppi_channel_enable(fram_3rd_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
     err = nrfx_ppi_channel_enable(fram_4th_write_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
    
    err = nrfx_ppi_channel_enable(fram_hibernate_timer_ppi_channel);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
		return;
	}
 
    err = nrfx_ppi_channel_assign(imu_trigger_disable_channel,
                                          timer_cc_event_addr,
                                          group_imu_disable_task_addr);
    if (err != NRFX_SUCCESS) {
		LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
		return;
	}
    // err = nrfx_ppi_channel_assign(fram_trigger_disable_channel,
    //                                       timer_fram_cc_event_addr,
    //                                       group_fram_disable_task_addr);
    // if (err != NRFX_SUCCESS) {
	// 	LOG_ERR("nrfx_ppi_channel_assign error: %08x", err);
	// 	return;
	// }

  
//    err_code = nrfx_ppi_channel_enable(trigger_ppi_channel);
//    APP_ERROR_CHECK(err_code);
 
//     err = nrfx_ppi_channel_enable(imu_trigger_disable_channel);
//     if (err != NRFX_SUCCESS) {
// 		LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
// 		return;
// 	}
    
    // disable for testing
    // err = nrfx_ppi_channel_enable(fram_trigger_disable_channel);
    // if (err != NRFX_SUCCESS) {
	// 	LOG_ERR("nrfx_ppi_channel_enable error: %08x", err);
	// 	return;
	// }

    nrfx_ppi_channel_include_in_group(imu_int1_trigger_ppi_channel, imu_trigger_group);
    // nrfx_ppi_channel_include_in_group(fram_spim_trigger_ppi_channel, fram_trigger_group);
    // nrfx_ppi_channel_include_in_group(fram_spim_end_trigger_ppi_channel, fram_trigger_group);
    
//    nrf_ppi_group_enable(trigger_group);

    nrfx_gpiote_out_task_enable(IMU_CS_PIN);  
    nrfx_gpiote_out_task_enable(FRAM_CS_PIN); 
}

RE: 4 second current spikes during sleep

Vidar Berg — Tue, 31 Jan 2023 09:09:56 GMT

Hi Wael,

Could you please try to use a GPIOTE PORT event to detect when the IMU's interrupt line is asserted and trigger the SPI task from your app instead of using PPI? You should see a lower floor current when using GPIOTE PORT event compared to when you have IN events enabled.

[153] GPIOTE: GPIOTE with low-power latency setting does not register IN events in System ON IDLE

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Mon, 30 Jan 2023 23:40:24 GMT

Hi Vidar,

Thank you for your reply. this makes complete sense. I now have another power consumption issue. My app does the following using PPI, SPIM, GPIOTE, and timers

the PPI configuration is as follow:

1) Upon receiving a GPIOTE trigger from an IMU(every 8.3 seconds), read its data (this is operating on a dedicated spi bus, SPIM0)

2) write a dummy read command to an FRAM IC to wake it up from hibernate state (SPIM1 bus)

3) trigger timer for 8ms from the start of the FRAM SPIM transaction(step 2)(period for FRAM to become stable from hibernate state)

4) write the WREN(write enable) command to the FRAM upon completion of the 8ms timer

5) write the (write command, address, data) to the FRAM

6) write the hibernate command to the FRAM

the multiple writes(aside from step 5) can NOT be combined as the bus CS pin needs to be toggled for the memory chip to accept the commands.

to do this, I used 2 spi buses and 4 timers(one timer mode for the 8ms delay and 4 counters)

In sum, my code works exactly as described and verified using oscilloscope.

my issue is after the first PPI transaction is triggered, something is consuming power and/or is staying on. has between 650 and 850us periods. please see the first plot below. Note: approx. 200uA of the 600uA is from my external peripherals on the board.

the 2nd plot shows this issue does not exist prior to the first PPI transaction.

I do not think its a timer issue. I have read that the EasyDMA does consume ~1.5mA but that should only be during transmission. and the frequency of these pulses do not correlate to any SPI transaction. I have not been able to isolate the cause of this and your time and effort would be greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Mon, 30 Jan 2023 08:56:32 GMT

Hi Wael,

[quote user="whazin"]1) will an external 32kHz crystal use less power? or[/quote]

The internal RC oscillator will lead to a slightly higher average current for the following reasons:

1. The Bluetooth controller will need to increase its RADIO RX listening windows to compensate for the additional clock drift compared to the LF crystal oscillator.

2. Requires periodic calibration,

3. RC oscillator has a higher run current.

You can estimate how much impact the clock source will have on your application (in terms of average power consumption) by using our online power profiler here:

Online Power Profiler for Bluetooth LE

[quote user="whazin"]

2) Since we know our device will be operating in a fairly temp controlled environment, what do you think would be wise settings to minimize power consumption but not get some egregious clock drift?

for example, do the cal every x number of deg change if possible. what do you think that x should be

or do it every x seconds(what do you think that x should be)

[/quote]

I think you can extend the interval to 8 seconds. From the PS:

Regards,

Vidar

RE: 4 second current spikes during sleep

Wael — Fri, 27 Jan 2023 16:48:07 GMT

Hi Vidar,

That seems to be it. I set the following

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP=0

CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD=2000

and period did change accordingly. please see plot.

So with that said, I have few questions.

1) will an external 32kHz crystal use less power? or

2) Since we know our device will be operating in a fairly temp controlled environment, what do you think would be wise settings to minimize power consumption but not get some egregious clock drift?

for example, do the cal every x number of deg change if possible. what do you think that x should be

or do it every x seconds(what do you think that x should be)

your help is greatly appreciated.

Regards,

Wael

RE: 4 second current spikes during sleep

Vidar Berg — Fri, 27 Jan 2023 14:04:32 GMT

Hello,

Please set CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_MAX_SKIP=0 and then try to adjust the CONFIG_CLOCK_CONTROL_NRF_CALIBRATION_PERIOD setting to see if it affects the interval of your current spike. The 2nd screenshot looks could be showing the clock calibration event (The 32K RC oscillator is calibrated periodically against the HF crystal oscillator).

Best regards,

Vidar