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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>ADC pin protection</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/96341/adc-pin-protection</link><description>Hi, 
 I am using the nRF5340 chip and I am switching a load with some parasitic capacitance (estimated at ~0.5nF) and I get voltage swings that could exceed Vdd and go below GND. I was wondering if the analog pins (AIN0-AIN7) have any built-in protection</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Wed, 08 Feb 2023 22:35:19 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/96341/adc-pin-protection" /><item><title>RE: ADC pin protection</title><link>https://devzone.nordicsemi.com/thread/409006?ContentTypeID=1</link><pubDate>Wed, 08 Feb 2023 22:35:19 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:bf2f0e26-24b1-4d6b-a726-19f17c77ed28</guid><dc:creator>Hieu</dc:creator><description>&lt;p&gt;Hi Chibit,&lt;/p&gt;
&lt;p&gt;Unfortunately, we do not release such details. I am very sorry for being unable to help.&lt;/p&gt;
&lt;p&gt;Hieu&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ADC pin protection</title><link>https://devzone.nordicsemi.com/thread/408724?ContentTypeID=1</link><pubDate>Wed, 08 Feb 2023 03:51:20 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:ae5e1ea2-e91a-447a-9a80-6e52bec05b1c</guid><dc:creator>ChiBit</dc:creator><description>&lt;p&gt;Hi Hieu,&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
&lt;p&gt;Thanks for the information. &amp;nbsp;However, it would be of great help if you could provide pin diagrams that show the pin protection and any details on the ESD protection, because I can use other techniques such as current limit resistors to solve the problem.&lt;/p&gt;
&lt;p&gt;Point of note is that I have excessive inductance in the circuit that&amp;nbsp;is causing the voltage swings and knowing the details of the pins and ESD protection can save me time.&lt;/p&gt;
&lt;p&gt;Your help would be greatly appreciated&lt;/p&gt;
&lt;p&gt;ChiBit&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: ADC pin protection</title><link>https://devzone.nordicsemi.com/thread/408719?ContentTypeID=1</link><pubDate>Wed, 08 Feb 2023 00:34:20 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:56365371-2737-4e78-854d-ad88d10bb2ce</guid><dc:creator>Hieu</dc:creator><description>&lt;p&gt;Hi ChiBit,&lt;/p&gt;
&lt;p&gt;There are some protections against ESD,&amp;nbsp;but&amp;nbsp;it is not&amp;nbsp;recommended to rely on this for input&amp;nbsp;outside of the absolute maximum ratings like you are describing.&lt;/p&gt;
&lt;p&gt;Below is a&amp;nbsp;quote from one of my seniors who is more experienced in this topic:&lt;/p&gt;
&lt;p style="padding-left:30px;"&gt;&lt;em&gt;&lt;span dir="ltr"&gt;If a pin voltage goes outside of VDD/VSS rails there is a risk of forward biasing internal p-n junctions, injecting noise on rails and distorting signal. So rule of thumb is that it&amp;#39;s not allowed.&amp;nbsp;[...] (It&amp;#39;s)&amp;nbsp;hard to tell where the limit is. We recommend to avoid it.&lt;/span&gt;&lt;/em&gt;&lt;/p&gt;
&lt;p&gt;&lt;span&gt;Hieu&lt;/span&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>