RE: use spi dma/easyDMA in a fifo manure, or cyclic queue

haakonsh — Wed, 15 Feb 2023 23:16:54 GMT

I suggest you use the EasyDMA list feature of the SPIM. This will require you to use the nrfx_spim driver and HAL directly instead of relying on zephyr's SPI device driver API, as you will want to handle CS/CONVST and SPIM's TASKS_START task with a TIMER.

The DMA list feature (RXD.LIST) increments the RXD.PTR after an EVENTS_END. The SPIM is then ready for the next transfer. You can disable the SPIM interrupts entirely, and let the ArrayList buffer fill up.

There is a catch however and that is that the SPIM does not know the size of the DMA list, nor have any mechanism to stop the SPIM from overflowing the DMA list if TASKS_START is triggered after the DMA list buffer is full.

You will therefore need to count the number of times EVENTS_STARTED has been triggered and manually update RXD.PTR to the next DMA list buffer.

This can be done by triggering a TIMER's TASKS_COUNT (in counter mode), on EVENTS_STARTED. And enabling a COMPARE event after 'X' EVENTS_STARTED, where 'X' is the size, in bytes, of your DMA list buffer divided by RXD.MAXCNT.

The TIMER's COMPARE interrupt will then signal that your DMA list buffer is about to be full and that you need update RXD.PTR with the address to the next DMA list buffer.

With this implementation the ADC sampling will have minimal impact with respect to scheduling overheads.