Configuring PIN 0.00 and P0.01 as GPIO

RE: Configuring PIN 0.00 and P0.01 as GPIO

Einar Thorsrud — Mon, 27 Mar 2023 08:01:39 GMT

Hi,

When I test the code with the configuration from your last post, this works as expected if I build for nrf5340dk_nrf5340_cpuapp. However, it does not work when building for nrf5340dk_nrf5340_cpuapp_ns. Is that what you are doing?

If so, the problem is that TF-M does respect CONFIG_SOC_ENABLE_LFXO=n. I have reported this to the maintainers. I do not have an elegant solution for now, but you can simply comment out these two lines in the implementation of spu_periph_init_cfg() in <SDK>/modules/tee/tf-m/trusted-firmware-m/platform/ext/target/nordic_nrf/common/nrf5340/target_cfg.c:

    /* Configure properly the XL1 and XL2 pins so that the low-frequency crystal
     * oscillator (LFXO) can be used.
     * This configuration can be done only from secure code, as otherwise those
     * register fields are not accessible.  That's why it is placed here.
     */
    nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
    nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);

RE: Configuring PIN 0.00 and P0.01 as GPIO

Surendra Amina — Fri, 24 Mar 2023 15:18:09 GMT

I have modified another board as well and redone the test. Result is same.The Pin P0.00 set to logic 0.

RE: Configuring PIN 0.00 and P0.01 as GPIO

Surendra Amina — Fri, 24 Mar 2023 15:09:32 GMT

I have checked solder bridge seems to be OK. I have checked SB1 and SB2, both are open. SB3 and SB4 are closed.

Did you get the chance to test the code?

prj.conf looks as follows

CONFIG_GPIO=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y
CONFIG_SOC_ENABLE_LFXO=n

RE: Configuring PIN 0.00 and P0.01 as GPIO

Einar Thorsrud — Fri, 24 Mar 2023 14:47:20 GMT

This looks good. Can you check with a multimeter or similar that the solder bridges that should have been cut are actually cut (so that they ar eventually open), and the once hat should be soldered are actually closed?

Edit: There is one other config that is needed that I forgot about, and that is CONFIG_SOC_ENABLE_LFXO=n. This is y by default.

RE: Configuring PIN 0.00 and P0.01 as GPIO

Surendra Amina — Fri, 24 Mar 2023 14:00:54 GMT

Please find the screen capture of PIN_CNF register

Please find the register dump in CSV as well

devzone.nordicsemi.com/.../Ozone_5F00_GPIO_5F00_Registers_5F00_1_5F00_230324.csv

Surendra

RE: Configuring PIN 0.00 and P0.01 as GPIO

Einar Thorsrud — Fri, 24 Mar 2023 13:16:39 GMT

Hi,

There is no other configuration that is needed. As long as you don't enable the 32.768 kHz crystal oscillator, the pins will be normal GPIO pins from the IC perspective. I did not get a change to test now, but can you check the GPIO registers from a debugger to see if the pins are configured as output and set and cleared as you would expect in the IC itself (at least seen from a debugger)?

PS: Your configuration is wrong, as you are trying to enable both the LFRC and synthesized (from HF clock). So you should remove the line in with CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y in you prj.conf. (That should not matter with regard to this issue, though.)