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<?xml-stylesheet type="text/xsl" href="https://devzone.nordicsemi.com/cfs-file/__key/system/syndication/rss.xsl" media="screen"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>nRF52832 SPI slave: expected idle current?</title><link>https://devzone.nordicsemi.com/f/nordic-q-a/99290/nrf52832-spi-slave-expected-idle-current</link><description>This old question ( ) raised the issue of excessive power consumption of the SPI slave peripheral compared to the datasheet. The datasheet has not been updated ( Online link ) and still states that the expected idle current is 1uA. 
 The reason I am looking</description><dc:language>en-US</dc:language><generator>Telligent Community 13</generator><lastBuildDate>Mon, 08 May 2023 15:05:11 GMT</lastBuildDate><atom:link rel="self" type="application/rss+xml" href="https://devzone.nordicsemi.com/f/nordic-q-a/99290/nrf52832-spi-slave-expected-idle-current" /><item><title>RE: nRF52832 SPI slave: expected idle current?</title><link>https://devzone.nordicsemi.com/thread/424346?ContentTypeID=1</link><pubDate>Mon, 08 May 2023 15:05:11 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:73529319-b762-44ff-8185-ae87e6b4a380</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Thank you for confirming, I just wanted to make sure that it was tested without any possible leakage on the GPIOs.&lt;/p&gt;
[quote user="JordanYates"]This didn&amp;#39;t change the results. Some boards 10uA and others 15uA with the code below, all boards 5uA without.[/quote]
&lt;p&gt;I have double-checked internally, and this is within the expected range. The added consumption will vary from chip-to-chip, but it shall be less than 20 uA in total.&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52832 SPI slave: expected idle current?</title><link>https://devzone.nordicsemi.com/thread/424129?ContentTypeID=1</link><pubDate>Mon, 08 May 2023 02:19:45 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:e2ab23ad-3786-4810-a11d-ec5f047c32de</guid><dc:creator>JordanYates</dc:creator><description>&lt;p&gt;Thanks for the input&amp;nbsp;&lt;span&gt;H&amp;aring;kon,&lt;/span&gt;&lt;/p&gt;
&lt;p&gt;I updated the test case to use a disconnected pin on the SoC, and configuring that pin to have an internal pull-up. This didn&amp;#39;t change the results. Some boards 10uA and others 15uA with the code below, all boards 5uA without.&lt;/p&gt;
&lt;p&gt;&lt;pre class="ui-code" data-mode="c_cpp"&gt;	const struct device *p0 = DEVICE_DT_GET(DT_NODELABEL(gpio0));
	uint8_t gpiote_ch;

	gpio_pin_configure(p0, 6, GPIO_INPUT | GPIO_PULL_UP);

	nrfx_gpiote_channel_alloc(&amp;amp;gpiote_ch);
	nrf_gpiote_event_configure(NRF_GPIOTE, gpiote_ch, 6, GPIOTE_CONFIG_POLARITY_HiToLo);
	nrf_gpiote_event_enable(NRF_GPIOTE, gpiote_ch);&lt;/pre&gt;&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item><item><title>RE: nRF52832 SPI slave: expected idle current?</title><link>https://devzone.nordicsemi.com/thread/423607?ContentTypeID=1</link><pubDate>Wed, 03 May 2023 15:00:14 GMT</pubDate><guid isPermaLink="false">137ad170-7792-4731-bb38-c0d22fbe4515:1a1ce535-cb7d-49d2-8d93-12d3d033dafd</guid><dc:creator>H&amp;#229;kon Alseth</dc:creator><description>&lt;p&gt;Hi,&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
[quote user=""]Firstly, I am looking for an &amp;quot;official&amp;quot; answer as to what the expected idle current is when SPIS is enabled but there is no CS activity.[/quote]
&lt;p&gt;It is as described in the link that you posted, an added current draw&amp;nbsp;similar to that of GPIOTE IN channel usage.&lt;/p&gt;
&lt;p&gt;It shall be less than 20 uA.&lt;/p&gt;
&lt;p&gt;&lt;/p&gt;
[quote user=""]Secondly, I am looking for a reason why I am seeing this 50/50 split in power consumption between boards. Errata 97 could potentially explain it, but only if the &amp;quot;high current consumption&amp;quot; varies between individual parts, and if the SPIS peripheral is actually using GPIOTE internally.[/quote]
&lt;p&gt;There are chip-to-chip variances on our devices that can account for smaller differences.&lt;/p&gt;
&lt;p&gt;Is the pin(s) itself pulled to a defined level at this point? If not, could you please try to add a pull-resistor on the CS pin?&lt;/p&gt;
&lt;p&gt;&amp;nbsp;&lt;/p&gt;
&lt;p&gt;Kind regards,&lt;/p&gt;
&lt;p&gt;Håkon&lt;/p&gt;&lt;div style="clear:both;"&gt;&lt;/div&gt;</description></item></channel></rss>