GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

zciwor — Tue, 16 May 2023 14:17:14 GMT

I am also very surprised at the large impact that had. Thank you for your help!

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

Stian Røed Hafskjold — Tue, 16 May 2023 09:28:16 GMT

Hi,

Thanks for reporting back. Sorry for not catching that, I was pretty sure that not configuring the sense-edge-mask (which makes the pin use the GPIOTE PORT event instead of the IN event) would only add about 10-15 uA, but I guess I was wrong. Anyways, I'm glad you were able to figure it out. I'll make the question public again (and I think you will have to approve somehow)

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

zciwor — Mon, 15 May 2023 17:08:13 GMT

I also removed my pin definitions from a previous comment to hopefully keep some of our information private. You can feel free to make this question public again for future reference.

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

zciwor — Mon, 15 May 2023 17:06:20 GMT

Hi Stian,

I was able to fix this! It is indeed a problem with the GPIO_INT_EDGE_* flag as described here: https://github.com/zephyrproject-rtos/zephyr/issues/28499

Migrating from 1.7.1 to 2.3.1 depreciated the CONFIG_GPIO_NRF_INT_EDGE_USING_SENSE=y flag that I had set.

Therefore, I needed to change my &gpio0 node to the following:

&gpio0 {

status = "okay";

sense-edge-mask = <0xffffffff>; // new for 2.3.0

};

This seemed to bring my power draw back down to normal levels.

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

Stian Røed Hafskjold — Mon, 15 May 2023 12:32:36 GMT

Hi, sorry for the late reply. I did take a look but could not find anything wrong. I tried to compare it with a project I have running here with the same pin interrupt configuration and the only difference I can see is that gpio0 seems to be missing the phandle property. Not sure if this is relevant or not but you can try to add this property in a .overlay file. &uart0 { phandle = < 0x12 >; };

Looking at the plots it seems like the floor current increases (as opposed to the active (internal) current, which by the internal regulator design is drawn in bursts) which indicates that the current is drawn through a resistive load on the VDD domain directly, not by the internal peripherals, but it is a bit difficult to see due the resolution of the plots. If you are able to provide zoomed in plots (50ms/div) with a 100,000 samples/sec resolution, it would be helpful. Also you can try to change the voltage and see if the current changes proportional to the voltage (which would indicate a resistive load).

If we assume the current is drawn directly from VDD; (500uA - 30 uA from the plots) = 470 uA difference could be the result of current flowing through two pullup/down resistors (3V / 13k Ohm) * 2 = 460 uA. One on each pin.
You can read the PIN_CNF[n] registers to check this hypothesis. Please post the output here:

nrfjprog --memrd 0x50000700 --n 0x80

Also if you can upload the hardware schematics it would be helpful.

I'm also wondering if it is the pin interrupt configuration that is causing the current consumption, or if it is the result of the pin interrupt handler starting up something else? Is it doing anything in the interrupt handler, or have you been able to reproduce this with simple code that just implements the pin interrupt functionality?

I think maybe the next step would be for me to reproduce the issue here. As long as I can see the same thing here, I would be able to find a solution for you. Would it be possible to run your code on a nRF52 DK, and still be able to reproduce the issue? If not, are you still able to provide the whole project code, then I can see if I'm able to get it to run somehow? Thanks

Best regards,
Stian

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

zciwor — Thu, 11 May 2023 14:37:56 GMT

Hi Stian,

Were you able to take a look at this issue? I am facing a release deadline quickly approaching.

Thanks,

Eric

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

zciwor — Tue, 09 May 2023 20:06:02 GMT

Thank you! Pin definitions for reference:

RE: GPIO_INT_EDGE_BOTH Resulting in ~500uA extra power draw

Stian Røed Hafskjold — Tue, 09 May 2023 15:46:21 GMT

Hi, sorry for the late reply. I tried your code snippet here, and I do not see any higher current consumption with NCS 2.3.0. Is it possible that the INT_PIN_1 is configured by some other peripherals in the device tree? Can you please upload the device tree build output file (build/zephyr/zephyr.dts) and also the file build/zephyr/.config, then I can help to check if everything looks ok. Thanks

Best regards,
Stian