Optimizing Power on nRF5340 SoC Designs

RE: Optimizing Power on nRF5340 SoC Designs

SNJY — Wed, 30 Apr 2025 00:52:31 GMT

Do these steps work for the nrf5340 Audio DK as well? When i disable log and serial using CONFIG_LOG=n
CONFIG_SERIAL=n, the existing functions in the sample applications fail when compiling.

RE: Optimizing Power on nRF5340 SoC Designs

Ben_Squar3d — Fri, 21 Feb 2025 11:30:12 GMT

Hi,

Before I hit every possible walls to trying to implement this with ncs 2.7.0, is this documentation still relevant on 2.7.0? Is there any changes or more up-to-date documentation? Thank you very much

RE: Optimizing Power on nRF5340 SoC Designs

Ilam — Thu, 06 Feb 2025 04:51:09 GMT

Hi guys,
I need to use nrf_pwr_mgmt.h file in nrf5340 project with zephyr. any guidance on how to include that directory will be helpful.

RE: Optimizing Power on nRF5340 SoC Designs

The_C_Advocate — Thu, 28 Mar 2024 14:45:59 GMT

Thank You, I was able to follow the article and achieve implementing a few pointers.

RE: Optimizing Power on nRF5340 SoC Designs

0x00 — Fri, 08 Sep 2023 07:50:43 GMT

Hi dears,

I'm trying to reduce the power consumption of a custom board with a nRF5340 SoC. The application is a sensor node with an ADC and the BT support to transfer sampled data to a PC (server with BT support).

The application requirement is that the module needs to sleep all time and 1 time/hour wake up to sample the analog entities and transfer with the BT connection. The SoC discovery with the ADC by SPI.

How can I implement that?

My understanding is:

- modifiy the project.conf
[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:969d7331-7757-4077-85a9-9136bd5dab47:type=text&text=CONFIG_PM%3Dy%0ACONFIG_PM_DEVICE%3Dy]

- include the headers for the PM control in the main.c
[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:15fd3454-8151-4a07-8a0b-f7fc04bc4282:type=text&text=%23include%20%3Czephyr%2Fpm%2Fpm.h%3E%0D%0A%23include%20%3Czephyr%2Fpm%2Fdevice.h%3E%0D%0A%23include%20%3Czephyr%2Fpm%2Fpolicy.h%3E]

- Prevent from System OFF (since that no hardware support for the wakeup is on board)

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:b8133bfc-9484-43b9-a31d-77146df02dc9:type=text&text=%09%2F%2A%20Prevent%20deep%20sleep%20%28system%20off%29%20from%20being%20entered%20%2A%2F%0D%0A%20%20%20%20pm_policy_state_lock_get%28PM_STATE_SOFT_OFF%29%3B]

- use the pm_device_action_run() function or somenthing lika that to switch the PM states.

My dubt is: without hardware events how can I use a RTC (I have a 32kHz crystal on board) or timers to put the in Sleep the module and how to WakeUp it after a certain time?

Many Thanks for your support and have a nice day,
Best Regards

RE: Optimizing Power on nRF5340 SoC Designs

Dker19 — Mon, 29 May 2023 16:27:28 GMT

I required the device should be run in low power mode when there is no work to do. so I gone through the state.h and found that there are different states. So I choose PM_STATE_RUNTIME_IDLE or PM_STATE_SUSPEND_TO_IDLE so just curious like if I select one of them then on some event how to wakeup the device to a normal state.

Also is there any best state other than PM_STATE_SOFT_OFF which help my device to save more power without losing its context?

Do I just need to disable/suspend the resources that are taking more power, this will save the power consumption of the battery. CPU will automatically go into sleep mode?

Can you please enlighten why there are different modes and When to use them? like, PM_STATE_RUNTIME_IDLE, PM_STATE_SUSPEND_TO_IDLE, PM_STATE_STANDBY and

PM_STATE_SUSPEND_TO_RAM.
Also how to use them?

RE: Optimizing Power on nRF5340 SoC Designs

Jester — Tue, 06 Sep 2022 14:14:50 GMT

Can you share the binaries of your experiment that proofs the low power behavior of the nrf on the DK ?
Not all of the Nordic users are Zephyr users, so the content of your zip file are not usable.
With your binaries we can at least proof our hardware setup is OK, if our current measurements end up in the same range as yours. If all currents are within limits with your binaries, and still too high with our software, then at least we know where to look.

RE: Optimizing Power on nRF5340 SoC Designs

Desmond G — Fri, 08 Jul 2022 07:00:32 GMT

How do I disable the high voltage regulator? Do I just use CONFIG_BOARD_ENABLE_DCDC_HV=n?

RE: Optimizing Power on nRF5340 SoC Designs

WesC — Tue, 07 Sep 2021 18:21:32 GMT

I recently added a project that was used for power verification. Below is a screen capture from the Power Profiler Kit 2 running the project on a nRF5340DK

RE: Optimizing Power on nRF5340 SoC Designs

Ursula Weinmann — Wed, 01 Sep 2021 14:52:48 GMT

Thank you for this article. Is there a sample SES project for the DevKit nRF5340-DK where the described measures or part of the described measures are implemented?