Essential pin planning guidelines for the nRF54L Series

RE: Essential pin planning guidelines for the nRF54L Series

devangs33 — Tue, 03 Mar 2026 18:18:00 GMT

Is there a similar document for nRF54H20 ?

RE: Essential pin planning guidelines for the nRF54L Series

humankey — Fri, 06 Feb 2026 15:54:51 GMT

I am designing an external battery-operated device using the nRF54L10 QFN48. I am constrained by the limited number of pins on Port 0 (5 pins) and trying to strictly follow the rule to "Match peripherals to their domains."

• I am using TWIM30 (LP domain) for a sensor on P0.

• I need to gate power to this sensor using a GPIO to save energy.

• I have run out of P0 pins.

If I place the Sensor VDD control on a P1 GPIO (Peri Domain) while keeping the I2C lines on P0 (LP Domain), I am concerned about leakage.

Questions:
1. If the PERI domain (P1) is powered down in System OFF/Sleep, but the LP domain (P0) remains active for wake-up monitoring, will the P1 GPIO hold its state, or will it cause the sensor VDD to float/drop, creating a leakage path from the P0 I2C pull-ups through the sensor?

2. Is it recommended to move non-wakeup assets (like LEDs) to P1 to free up P0 for the Sensor VDD, ensuring the entire sensor interface remains within the LP domain?

RE: Essential pin planning guidelines for the nRF54L Series

odin huang — Tue, 25 Nov 2025 03:10:13 GMT

Dear Nordic,

The peripheral-to-pin connection matrix for the nRF54L Series should be clearly presented in a matrix/table format within the datasheet. I cannot ascertain from the current datasheet that the PWM output pins are restricted to Port 1 (P1). It merely states that all P1 pins can be used, but fails to clarify why Port 0 (P0) and Port 2 (P2) cannot be used.

This usage and restriction represent a departure from previous nRF52/nRF53 series devices. Therefore, a clear and explicit Peripheral-to-Pin Configuration Matrix Table is needed on the very first page of the peripheral section in the manual for quick and easy reference. This is similar to the pin/peripheral matrix tables found in STM32 datasheets, which allow for rapid, clear distinction, helping to prevent errors in pin selection, especially when selecting peripherals that utilize shared pins.

RE: Essential pin planning guidelines for the nRF54L Series

leox — Thu, 10 Jul 2025 23:26:58 GMT

The pin planner is good, would be better if able to export to a device tree overlay format instead json, so able to use in the project/custom board directly.

RE: Essential pin planning guidelines for the nRF54L Series

Ingfu — Thu, 26 Jun 2025 06:15:16 GMT

What happens, if I use a non-clock pin as a clock pin? Could it work at low frequencies?

RE: Essential pin planning guidelines for the nRF54L Series

Fridtjof — Mon, 23 Jun 2025 11:36:48 GMT

Dear Nordic

Why do I have to go to this blog post to find the following information?

P2 pins cannot wake the system from sleep, and it does not include the GPIO SENSE or DETECT mechanism or GPIOTE functionality. This means that interrupt support is not available on P2 pins when they are configured as general-purpose GPIO.

There is no mention of this in nrf54L15 PS section 8.8 - GPIO, or in the pin tables in section 10. And the only feedback the user gets is that gpio_pin_interrupt_configure_dt() returns -ENOTSUP.