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Adding new IRQn to vector table on NRF52/Cortex M4

Hi there,

I am currently wondering if the following is possible?

As stated by the Cortex M4 reference manual states that a system can have 200+ seperate handlers within the vector table. From reading through the NRF52832 datasheet it states that 38 are actually used, this is also backed up within nrf52.h

Below can the last one can be seen.

FPU_IRQn =  38               /*!<  38  FPU

Now I was wondering would it be possible for me to extend this enum and add the following:

CUSTOM_IRQn = 39

I have added another handler procedure for this and adjusted the .s file so the reserved entry straight after FPU_IRQn now points to my handler procedure.

To test to see if this works I've been attempting to trigger the interrupt using software interrupts as follows:

NVIC_SetPriority(CUSTOM_IRQn, 10);
NVIC_EnableIRQ(CUSTOM_IRQn);

NVIC->STIR = CUSTOM_IRQn;

I breakpoint on my handler procedure and it is never called. Is adding custom/new interrupt vectors even possible?

  • No it's not possible. The number of implemented IRQs is a manufacturer choice, there's a maximum, the implementer chooses how many to actually implement.

    If you look at the CPU information in the nRF52 datasheet you will see that 37 vectors are implemented in the NVIC on this chip.

  • What is the point of the 'reserved' elements within the vector table at the end? Are they just for alignment?

            DATA
    
    __vector_table
            DCD     sfe(CSTACK)
            DCD     Reset_Handler
            DCD     NMI_Handler
            DCD     HardFault_Handler
            DCD     MemoryManagement_Handler
            DCD     BusFault_Handler
            DCD     UsageFault_Handler
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     SVC_Handler
            DCD     DebugMon_Handler
            DCD     0                         ; Reserved
            DCD     PendSV_Handler
            DCD     SysTick_Handler
    
            ; External Interrupts
            DCD     POWER_CLOCK_IRQHandler
            DCD     RADIO_IRQHandler
            DCD     UARTE0_UART0_IRQHandler
            DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
            DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
            DCD     NFCT_IRQHandler
            DCD     GPIOTE_IRQHandler
            DCD     SAADC_IRQHandler
            DCD     TIMER0_IRQHandler
            DCD     TIMER1_IRQHandler
            DCD     TIMER2_IRQHandler
            DCD     RTC0_IRQHandler
            DCD     TEMP_IRQHandler
            DCD     RNG_IRQHandler
            DCD     ECB_IRQHandler
            DCD     CCM_AAR_IRQHandler
            DCD     WDT_IRQHandler
            DCD     RTC1_IRQHandler
            DCD     QDEC_IRQHandler
            DCD     COMP_LPCOMP_IRQHandler
            DCD     SWI0_EGU0_IRQHandler
            DCD     SWI1_EGU1_IRQHandler
            DCD     SWI2_EGU2_IRQHandler
            DCD     SWI3_EGU3_IRQHandler
            DCD     SWI4_EGU4_IRQHandler
            DCD     SWI5_EGU5_IRQHandler
            DCD     TIMER3_IRQHandler
            DCD     TIMER4_IRQHandler
            DCD     PWM0_IRQHandler
            DCD     PDM_IRQHandler
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     MWU_IRQHandler
            DCD     PWM1_IRQHandler
            DCD     PWM2_IRQHandler
            DCD     SPIM2_SPIS2_SPI2_IRQHandler
            DCD     RTC2_IRQHandler
            DCD     I2S_IRQHandler
            DCD     FPU_IRQHandler
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
            DCD     0                         ; Reserved
    
    __Vectors_End
    __Vectors                           EQU   __vector_table
    __Vectors_Size                      EQU   __Vectors_End - __Vectors
    
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