nRF52 driver, nrf_drv_spis_buffers_set(): is max buffer size uint8_t?

[FI]

Hello,

I am trying to get SPIS EasyDMA to work. Currently the SPIS MISO response with high when the CS is pulled low by another master device, but no correct data present on the MISO.

The SPIS is setup via:

0. Enable SPIS0 in config

1. define SPIS0 instance with NRF_DRV_SPIS_INSTANCE()

2. get a config with NRF_DRV_SPIS_DEFAULT_CONFIG, and plug in the desired settings

3. initialize using nrf_drv_spis_init(), I am using a placeholder event handle

4. the I go to another route from the drivers, so I am doing &spis->TXD.MAXCNT = 1080, and &spis->TXD.PTR = (int32_t) buf

5. I disabled the interrupts with nrf_spis_int_disable()

I am not using the nrf_drv_spis_buffers_set(), because it only take uint8_t as buffer length, while I am hoping to transfer a buffer of 1080 is one setting. Is this definition consistent with HW capability, so it is limited to 255? How about List? How to work with that on the length?

Right now my code is not working right yet, again, the MISO pulls high when the CS is driven low from external, SPI clock present, at 1 MHz. Just not seeing the right data which I am also observing through UART locally via same pointer to the buffers.

If I stitch in the nrf_drv_spis_buffers_set() call in the data process routine, the current error code is 0x08, invalid state.

So please advise before the weekend to help me to have more fun making progress! Thanks.

FI

[FI]

I saw this post. Please confirm that the max buffer length for SPIS is 255. Though I was hopeful it could be larger. Thanks

devzone.nordicsemi.com/.../

[MartinBL]

Hi,

The SPIS TXD.MAXCNT and RXD.MAXCNT registers can only hold 8 bit values. I.e. the maximum number of bytes in the transmit and receive buffers is only 255.

[SRA]

Is there a technical reason that someone would not want to increase this SPI transfer size? I think 255 bytes is a reasonable SPI transfer size and probably hits a sweet spot between bandwidth and potential corruption but figured I'd ask.

Is this a potential hardware or the EasyDMA limit?

[FI]

This is verified. The Max size of the buffer is 255. So, for larger buffer size, I am just segmenting this down and implemented a flow control. Not a big deal, but it could be sweeter, since it is already pretty bare minimum to get it setup and run.

Thanks for the support!

[MartinBL]

Good question. I couldn't find a definitive answer, but I am told that it is partly due to legacy reasons and partly because of hardware restrictions. Originally we designed the SPIS module with the max count registers 8 bits wide and any changes we make will require time and money for testing. Increasing the register will also require slightly more physical space in hardware and draw more power. You could argue though, that the extra space and current would be tiny, but you have got to draw the line somewhere.