Branch data Line data Source code
1 : : /*
2 : : * Copyright (c) 2019 - 2022, Nordic Semiconductor ASA
3 : : * All rights reserved.
4 : : *
5 : : * SPDX-License-Identifier: BSD-3-Clause
6 : : *
7 : : * Redistribution and use in source and binary forms, with or without
8 : : * modification, are permitted provided that the following conditions are met:
9 : : *
10 : : * 1. Redistributions of source code must retain the above copyright notice, this
11 : : * list of conditions and the following disclaimer.
12 : : *
13 : : * 2. Redistributions in binary form must reproduce the above copyright
14 : : * notice, this list of conditions and the following disclaimer in the
15 : : * documentation and/or other materials provided with the distribution.
16 : : *
17 : : * 3. Neither the name of the copyright holder nor the names of its
18 : : * contributors may be used to endorse or promote products derived from this
19 : : * software without specific prior written permission.
20 : : *
21 : : * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 : : * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 : : * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 : : * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 : : * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 : : * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 : : * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 : : * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 : : * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 : : * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 : : * POSSIBILITY OF SUCH DAMAGE.
32 : : */
33 : :
34 : : #ifndef NRFX_GPPI_H
35 : : #define NRFX_GPPI_H
36 : :
37 : : #include <nrfx.h>
38 : :
39 : : #if NRFX_CHECK(NRFX_DPPI_ENABLED)
40 : : #include <nrfx_dppi.h>
41 : : #endif
42 : :
43 : : #if NRFX_CHECK(NRFX_PPI_ENABLED)
44 : : #include <nrfx_ppi.h>
45 : : #endif
46 : :
47 : : #ifdef __cplusplus
48 : : extern "C" {
49 : : #endif
50 : :
51 : : /**
52 : : * @defgroup nrfx_gppi Generic PPI layer
53 : : * @{
54 : : * @ingroup nrfx
55 : : * @ingroup nrf_dppi
56 : : * @ingroup nrf_ppi
57 : : *
58 : : * @brief Helper layer that provides the common functionality of PPI and DPPI drivers.
59 : : *
60 : : * Use PPI and DPPI drivers directly.
61 : : * This layer is provided only to help create generic code that can be built
62 : : * for SoCs equipped with either of these peripherals. When using this layer,
63 : : * take into account that there are significant differences between the PPI and DPPI
64 : : * interfaces that affect the behavior of this layer.
65 : : *
66 : : * One difference is that PPI allows associating of one task or event with
67 : : * more than one channel, whereas DPPI does not allow this. In DPPI, the second
68 : : * association overwrites the first one. Consequently, this helper layer cannot
69 : : * be used in applications that need to connect a task or event to multiple
70 : : * channels.
71 : : *
72 : : * Another difference is that in DPPI one channel can be associated with
73 : : * multiple tasks and multiple events, while in PPI this is not possible (with
74 : : * the exception of the association of a second task as a fork). Because of
75 : : * this difference, it is important to clear the previous endpoints of the channel that
76 : : * is to be reused with some different ones. Otherwise, the behavior of this
77 : : * helper layer will be different, depending on the actual interface used:
78 : : * in DPPI the channel configuration will be extended with the new endpoints, and
79 : : * in PPI the new endpoints will replace the previous ones.
80 : : */
81 : :
82 : : #if defined(PPI_PRESENT)
83 : : #include <hal/nrf_ppi.h>
84 : :
85 : : typedef enum
86 : : {
87 : : NRFX_GPPI_CHANNEL_GROUP0 = NRF_PPI_CHANNEL_GROUP0,
88 : : NRFX_GPPI_CHANNEL_GROUP1 = NRF_PPI_CHANNEL_GROUP1,
89 : : NRFX_GPPI_CHANNEL_GROUP2 = NRF_PPI_CHANNEL_GROUP2,
90 : : NRFX_GPPI_CHANNEL_GROUP3 = NRF_PPI_CHANNEL_GROUP3,
91 : : #if (PPI_GROUP_NUM > 4)
92 : : NRFX_GPPI_CHANNEL_GROUP4 = NRF_PPI_CHANNEL_GROUP4,
93 : : NRFX_GPPI_CHANNEL_GROUP5 = NRF_PPI_CHANNEL_GROUP5,
94 : : #endif
95 : : } nrfx_gppi_channel_group_t;
96 : :
97 : : typedef enum
98 : : {
99 : : NRFX_GPPI_TASK_CHG0_EN = NRF_PPI_TASK_CHG0_EN,
100 : : NRFX_GPPI_TASK_CHG0_DIS = NRF_PPI_TASK_CHG0_DIS,
101 : : NRFX_GPPI_TASK_CHG1_EN = NRF_PPI_TASK_CHG1_EN,
102 : : NRFX_GPPI_TASK_CHG1_DIS = NRF_PPI_TASK_CHG1_DIS,
103 : : NRFX_GPPI_TASK_CHG2_EN = NRF_PPI_TASK_CHG2_EN,
104 : : NRFX_GPPI_TASK_CHG2_DIS = NRF_PPI_TASK_CHG2_DIS,
105 : : NRFX_GPPI_TASK_CHG3_EN = NRF_PPI_TASK_CHG3_EN,
106 : : NRFX_GPPI_TASK_CHG3_DIS = NRF_PPI_TASK_CHG3_DIS,
107 : : #if (PPI_GROUP_NUM > 4)
108 : : NRFX_GPPI_TASK_CHG4_EN = NRF_PPI_TASK_CHG4_EN,
109 : : NRFX_GPPI_TASK_CHG4_DIS = NRF_PPI_TASK_CHG4_DIS,
110 : : NRFX_GPPI_TASK_CHG5_EN = NRF_PPI_TASK_CHG5_EN,
111 : : NRFX_GPPI_TASK_CHG5_DIS = NRF_PPI_TASK_CHG5_DIS
112 : : #endif
113 : : } nrfx_gppi_task_t;
114 : :
115 : : #elif defined(DPPI_PRESENT)
116 : : #include <hal/nrf_dppi.h>
117 : :
118 : : typedef enum
119 : : {
120 : : NRFX_GPPI_CHANNEL_GROUP0 = NRF_DPPI_CHANNEL_GROUP0,
121 : : NRFX_GPPI_CHANNEL_GROUP1 = NRF_DPPI_CHANNEL_GROUP1,
122 : : NRFX_GPPI_CHANNEL_GROUP2 = NRF_DPPI_CHANNEL_GROUP2,
123 : : NRFX_GPPI_CHANNEL_GROUP3 = NRF_DPPI_CHANNEL_GROUP3,
124 : : NRFX_GPPI_CHANNEL_GROUP4 = NRF_DPPI_CHANNEL_GROUP4,
125 : : NRFX_GPPI_CHANNEL_GROUP5 = NRF_DPPI_CHANNEL_GROUP5,
126 : : } nrfx_gppi_channel_group_t;
127 : :
128 : : typedef enum
129 : : {
130 : : NRFX_GPPI_TASK_CHG0_EN = NRF_DPPI_TASK_CHG0_EN,
131 : : NRFX_GPPI_TASK_CHG0_DIS = NRF_DPPI_TASK_CHG0_DIS,
132 : : NRFX_GPPI_TASK_CHG1_EN = NRF_DPPI_TASK_CHG1_EN,
133 : : NRFX_GPPI_TASK_CHG1_DIS = NRF_DPPI_TASK_CHG1_DIS,
134 : : NRFX_GPPI_TASK_CHG2_EN = NRF_DPPI_TASK_CHG2_EN,
135 : : NRFX_GPPI_TASK_CHG2_DIS = NRF_DPPI_TASK_CHG2_DIS,
136 : : NRFX_GPPI_TASK_CHG3_EN = NRF_DPPI_TASK_CHG3_EN,
137 : : NRFX_GPPI_TASK_CHG3_DIS = NRF_DPPI_TASK_CHG3_DIS,
138 : : NRFX_GPPI_TASK_CHG4_EN = NRF_DPPI_TASK_CHG4_EN,
139 : : NRFX_GPPI_TASK_CHG4_DIS = NRF_DPPI_TASK_CHG4_DIS,
140 : : NRFX_GPPI_TASK_CHG5_EN = NRF_DPPI_TASK_CHG5_EN,
141 : : NRFX_GPPI_TASK_CHG5_DIS = NRF_DPPI_TASK_CHG5_DIS
142 : : } nrfx_gppi_task_t;
143 : :
144 : : #elif defined(__NRFX_DOXYGEN__)
145 : :
146 : : /** @brief Generic PPI channel groups. */
147 : : typedef enum
148 : : {
149 : : NRFX_GPPI_CHANNEL_GROUP0, /**< Channel group 0.*/
150 : : NRFX_GPPI_CHANNEL_GROUP1, /**< Channel group 1.*/
151 : : NRFX_GPPI_CHANNEL_GROUP2, /**< Channel group 2.*/
152 : : NRFX_GPPI_CHANNEL_GROUP3, /**< Channel group 3.*/
153 : : NRFX_GPPI_CHANNEL_GROUP4, /**< Channel group 4.*/
154 : : NRFX_GPPI_CHANNEL_GROUP5, /**< Channel group 5.*/
155 : : } nrfx_gppi_channel_group_t;
156 : :
157 : : /** @brief Generic PPI tasks. */
158 : : typedef enum
159 : : {
160 : : NRFX_GPPI_TASK_CHG0_EN, /**< Task for enabling channel group 0 */
161 : : NRFX_GPPI_TASK_CHG0_DIS, /**< Task for disabling channel group 0 */
162 : : NRFX_GPPI_TASK_CHG1_EN, /**< Task for enabling channel group 1 */
163 : : NRFX_GPPI_TASK_CHG1_DIS, /**< Task for disabling channel group 1 */
164 : : NRFX_GPPI_TASK_CHG2_EN, /**< Task for enabling channel group 2 */
165 : : NRFX_GPPI_TASK_CHG2_DIS, /**< Task for disabling channel group 2 */
166 : : NRFX_GPPI_TASK_CHG3_EN, /**< Task for enabling channel group 3 */
167 : : NRFX_GPPI_TASK_CHG3_DIS, /**< Task for disabling channel group 3 */
168 : : NRFX_GPPI_TASK_CHG4_EN, /**< Task for enabling channel group 4 */
169 : : NRFX_GPPI_TASK_CHG4_DIS, /**< Task for disabling channel group 4 */
170 : : NRFX_GPPI_TASK_CHG5_EN, /**< Task for enabling channel group 5 */
171 : : NRFX_GPPI_TASK_CHG5_DIS, /**< Task for disabling channel group 5 */
172 : : } nrfx_gppi_task_t;
173 : : #endif // defined(__NRFX_DOXYGEN__)
174 : :
175 : : /**
176 : : * @brief Function for checking if a given channel is enabled.
177 : : *
178 : : * @param[in] channel Channel to check.
179 : : *
180 : : * @retval true The channel is enabled.
181 : : * @retval false The channel is not enabled.
182 : : */
183 : : __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel);
184 : :
185 : : /** @brief Function for disabling all channels. */
186 : : __STATIC_INLINE void nrfx_gppi_channels_disable_all(void);
187 : :
188 : : /**
189 : : * @brief Function for enabling multiple channels.
190 : : *
191 : : * The bits in @c mask value correspond to particular channels. This means that
192 : : * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1, etc.
193 : : *
194 : : * @param[in] mask Channel mask.
195 : : */
196 : : __STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask);
197 : :
198 : : /**
199 : : * @brief Function for disabling multiple channels.
200 : : *
201 : : * The bits in @c mask value correspond to particular channels. This means that
202 : : * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1, etc.
203 : : *
204 : : * @param[in] mask Channel mask.
205 : : */
206 : : __STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask);
207 : :
208 : : /**
209 : : * @brief Function for associating a given channel with the specified event register.
210 : : *
211 : : * This function sets the DPPI publish configuration for a given event
212 : : * or sets the PPI event endpoint register.
213 : : *
214 : : * @param[in] channel Channel to which to assign the event.
215 : : * @param[in] eep Address of the event register.
216 : : */
217 : : __STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep);
218 : :
219 : : /**
220 : : * @brief Function for associating a given channel with the specified task register.
221 : : *
222 : : * This function sets the DPPI subscribe configuration for a given task
223 : : * or sets the PPI task endpoint register.
224 : : *
225 : : * @param[in] channel Channel to which to assign the task.
226 : : * @param[in] tep Address of the task register.
227 : : */
228 : : __STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep);
229 : :
230 : : /**
231 : : * @brief Function for setting up the event and task endpoints for a given channel.
232 : : *
233 : : * @param[in] channel Channel to which the given endpoints are assigned.
234 : : * @param[in] eep Address of the event register.
235 : : * @param[in] tep Address of the task register.
236 : : */
237 : : __STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
238 : : uint32_t eep,
239 : : uint32_t tep);
240 : :
241 : : /**
242 : : * @brief Function for clearing the DPPI publish configuration for a given event
243 : : * register or for clearing the PPI event endpoint register.
244 : : *
245 : : * @param[in] channel Channel for which to clear the event endpoint. Not used in DPPI.
246 : : * @param[in] eep Address of the event register. Not used in PPI.
247 : : */
248 : : __STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep);
249 : :
250 : : /**
251 : : * @brief Function for clearing the DPPI subscribe configuration for a given task
252 : : * register or for clearing the PPI task endpoint register.
253 : : *
254 : : * @param[in] channel Channel from which to disconnect the task enpoint. Not used in DPPI.
255 : : * @param[in] tep Address of the task register. Not used in PPI.
256 : : */
257 : : __STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep);
258 : :
259 : :
260 : : #if defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
261 : : /**
262 : : * @brief Function for setting up the task endpoint for a given PPI fork or for
263 : : * associating the DPPI channel with an additional task register.
264 : : *
265 : : * @param[in] channel Channel to which the given fork endpoint is assigned.
266 : : * @param[in] fork_tep Address of the task register.
267 : : */
268 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep);
269 : :
270 : : /**
271 : : * @brief Function for clearing the task endpoint for a given PPI fork or for clearing
272 : : * the DPPI subscribe register.
273 : : *
274 : : * @param[in] channel Channel for which to clear the fork endpoint. Not used in DPPI.
275 : : * @param[in] fork_tep Address of the task register. Not used in PPI.
276 : : */
277 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep);
278 : : #endif // defined(PPI_FEATURE_FORKS_PRESENT) || defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
279 : :
280 : : /**
281 : : * @brief Function for including multiple channels in a channel group.
282 : : *
283 : : * @param[in] channel_mask Channels to be included in the group.
284 : : * @param[in] channel_group Channel group.
285 : : */
286 : : __STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
287 : : nrfx_gppi_channel_group_t channel_group);
288 : :
289 : : /**
290 : : * @brief Function for removing multiple channels from a channel group.
291 : : *
292 : : * @param[in] channel_mask Channels to be removed from the group.
293 : : * @param[in] channel_group Channel group.
294 : : */
295 : : __STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
296 : : nrfx_gppi_channel_group_t channel_group);
297 : :
298 : : /**
299 : : * @brief Function for removing all channels from a channel group.
300 : : *
301 : : * @param[in] channel_group Channel group.
302 : : */
303 : : __STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group);
304 : :
305 : : /**
306 : : * @brief Function for enabling a channel group.
307 : : *
308 : : * @param[in] channel_group Channel group.
309 : : */
310 : : __STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group);
311 : :
312 : : /**
313 : : * @brief Function for disabling a group.
314 : : *
315 : : * @param[in] channel_group Channel group.
316 : : */
317 : : __STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group);
318 : :
319 : : /**
320 : : * @brief Function for activating a task.
321 : : *
322 : : * @param[in] task Task to be activated.
323 : : */
324 : : __STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task);
325 : :
326 : : /**
327 : : * @brief Function for returning the address of a specific task register.
328 : : *
329 : : * @param[in] task PPI or DPPI task.
330 : : *
331 : : * @return Address of the requested task register.
332 : : */
333 : : __STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t task);
334 : :
335 : : /**
336 : : * @brief Function for returning the address of a channel group disable task.
337 : : *
338 : : * @param[in] group Channel group.
339 : : *
340 : : * @return Disable task address of the specified group.
341 : : */
342 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group);
343 : :
344 : : /**
345 : : * @brief Function for returning the address of a channel group enable task.
346 : : *
347 : : * @param[in] group Channel group.
348 : : *
349 : : * @return Enable task address of the specified group.
350 : : */
351 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group);
352 : :
353 : : /**
354 : : * @brief Function for allocating a channel.
355 : : *
356 : : * @param[out] p_channel After successful allocation, index of the allocated channel.
357 : : *
358 : : * @retval NRFX_SUCCESS Channel was successfully allocated.
359 : : * @retval NRFX_ERROR_NO_MEM There is no available channel to be used.
360 : : * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled.
361 : : */
362 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel);
363 : :
364 : : /**
365 : : * @brief Function for freeing a channel.
366 : : *
367 : : * @param[in] channel (D)PPI channel to be freed.
368 : : *
369 : : * @retval NRFX_SUCCESS The channel was successfully freed.
370 : : * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated or
371 : : * is not user-configurable.
372 : : * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled.
373 : : */
374 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel);
375 : :
376 : : /**
377 : : * @brief Function for allocating a channel group.
378 : : *
379 : : * @param[out] p_group Pointer to the (D)PPI channel group that has been allocated.
380 : : *
381 : : * @retval NRFX_SUCCESS The channel group was successfully allocated.
382 : : * @retval NRFX_ERROR_NO_MEM There is no available channel group to be used.
383 : : * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled.
384 : : */
385 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group);
386 : :
387 : : /**
388 : : * @brief Function for freeing a channel group.
389 : : *
390 : : * @param[in] group (D)PPI channel group to be freed.
391 : : *
392 : : * @retval NRFX_SUCCESS The channel was successfully freed.
393 : : * @retval NRFX_ERROR_INVALID_PARAM The specified channel is not allocated or
394 : : * is not user-configurable.
395 : : * @retval NRFX_ERROR_NOT_SUPPORTED Driver is not enabled.
396 : : */
397 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group);
398 : : /** @} */
399 : :
400 : : #if defined(PPI_PRESENT)
401 : :
402 : : __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel)
403 : : {
404 : : return (nrf_ppi_channel_enable_get(NRF_PPI, (nrf_ppi_channel_t)channel) ==
405 : : NRF_PPI_CHANNEL_ENABLED);
406 : : }
407 : :
408 : : __STATIC_INLINE void nrfx_gppi_channels_disable_all(void)
409 : : {
410 : : nrf_ppi_channels_disable_all(NRF_PPI);
411 : : }
412 : :
413 : : __STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask)
414 : : {
415 : : nrf_ppi_channels_enable(NRF_PPI, mask);
416 : : }
417 : :
418 : : __STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask)
419 : : {
420 : : nrf_ppi_channels_disable(NRF_PPI, mask);
421 : : }
422 : :
423 : : __STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
424 : : {
425 : : nrf_ppi_event_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, eep);
426 : : }
427 : :
428 : : __STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
429 : : {
430 : : nrf_ppi_task_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, tep);
431 : : }
432 : :
433 : : __STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
434 : : uint32_t eep,
435 : : uint32_t tep)
436 : : {
437 : : nrf_ppi_channel_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, eep, tep);
438 : : }
439 : :
440 : : __STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep)
441 : : {
442 : : (void)eep;
443 : : nrf_ppi_event_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, 0);
444 : : }
445 : :
446 : : __STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep)
447 : : {
448 : : (void)tep;
449 : : nrf_ppi_task_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, 0);
450 : : }
451 : :
452 : : #if defined(PPI_FEATURE_FORKS_PRESENT)
453 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep)
454 : : {
455 : : nrf_ppi_fork_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, fork_tep);
456 : : }
457 : :
458 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep)
459 : : {
460 : : (void)fork_tep;
461 : : nrf_ppi_fork_endpoint_setup(NRF_PPI, (nrf_ppi_channel_t)channel, 0);
462 : : }
463 : : #endif
464 : :
465 : : __STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
466 : : nrfx_gppi_channel_group_t channel_group)
467 : : {
468 : : nrf_ppi_channels_include_in_group(NRF_PPI,
469 : : channel_mask,
470 : : (nrf_ppi_channel_group_t)channel_group);
471 : : }
472 : :
473 : : __STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
474 : : nrfx_gppi_channel_group_t channel_group)
475 : : {
476 : : nrf_ppi_channels_remove_from_group(NRF_PPI,
477 : : channel_mask,
478 : : (nrf_ppi_channel_group_t)channel_group);
479 : : }
480 : :
481 : : __STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group)
482 : : {
483 : : nrf_ppi_group_clear(NRF_PPI, (nrf_ppi_channel_group_t)channel_group);
484 : : }
485 : :
486 : : __STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group)
487 : : {
488 : : nrf_ppi_group_enable(NRF_PPI, (nrf_ppi_channel_group_t)channel_group);
489 : : }
490 : :
491 : : __STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group)
492 : : {
493 : : nrf_ppi_group_disable(NRF_PPI, (nrf_ppi_channel_group_t)channel_group);
494 : : }
495 : :
496 : : __STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task)
497 : : {
498 : : nrf_ppi_task_trigger(NRF_PPI, (nrf_ppi_task_t)task);
499 : : }
500 : :
501 : : __STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t task)
502 : : {
503 : : return (uint32_t)nrf_ppi_task_address_get(NRF_PPI, (nrf_ppi_task_t)task);
504 : : }
505 : :
506 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group)
507 : : {
508 : : return (nrfx_gppi_task_t)nrf_ppi_group_disable_task_get(NRF_PPI, (uint8_t)group);
509 : : }
510 : :
511 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group)
512 : : {
513 : : return (nrfx_gppi_task_t)nrf_ppi_group_enable_task_get(NRF_PPI, (uint8_t)group);
514 : : }
515 : :
516 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel)
517 : : {
518 : : #if NRFX_CHECK(NRFX_PPI_ENABLED)
519 : : return nrfx_ppi_channel_alloc((nrf_ppi_channel_t *)p_channel);
520 : : #else
521 : : (void)p_channel;
522 : : return NRFX_ERROR_NOT_SUPPORTED;
523 : : #endif
524 : : }
525 : :
526 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel)
527 : : {
528 : : #if NRFX_CHECK(NRFX_PPI_ENABLED)
529 : : return nrfx_ppi_channel_free((nrf_ppi_channel_t)channel);
530 : : #else
531 : : (void)channel;
532 : : return NRFX_ERROR_NOT_SUPPORTED;
533 : : #endif
534 : : }
535 : :
536 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group)
537 : : {
538 : : #if NRFX_CHECK(NRFX_PPI_ENABLED)
539 : : return nrfx_ppi_group_alloc((nrf_ppi_channel_group_t *)p_group);
540 : : #else
541 : : (void)p_group;
542 : : return NRFX_ERROR_NOT_SUPPORTED;
543 : : #endif
544 : : }
545 : :
546 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group)
547 : : {
548 : : #if NRFX_CHECK(NRFX_PPI_ENABLED)
549 : : return nrfx_ppi_group_free((nrf_ppi_channel_group_t)group);
550 : : #else
551 : : (void)group;
552 : : return NRFX_ERROR_NOT_SUPPORTED;
553 : : #endif
554 : : }
555 : : #elif defined(DPPI_PRESENT)
556 : :
557 : : __STATIC_INLINE bool nrfx_gppi_channel_check(uint8_t channel)
558 : : {
559 : : return nrf_dppi_channel_check(NRF_DPPIC, channel);
560 : : }
561 : :
562 : : __STATIC_INLINE void nrfx_gppi_channels_disable_all(void)
563 : : {
564 : : nrf_dppi_channels_disable_all(NRF_DPPIC);
565 : : }
566 : :
567 : 1 : __STATIC_INLINE void nrfx_gppi_channels_enable(uint32_t mask)
568 : : {
569 : 1 : nrf_dppi_channels_enable(NRF_DPPIC, mask);
570 : 1 : }
571 : :
572 : : __STATIC_INLINE void nrfx_gppi_channels_disable(uint32_t mask)
573 : : {
574 : : nrf_dppi_channels_disable(NRF_DPPIC, mask);
575 : : }
576 : :
577 : : __STATIC_INLINE void nrfx_gppi_task_trigger(nrfx_gppi_task_t task)
578 : : {
579 : : nrf_dppi_task_trigger(NRF_DPPIC, (nrf_dppi_task_t)task);
580 : : }
581 : :
582 : 1 : __STATIC_INLINE void nrfx_gppi_event_endpoint_setup(uint8_t channel, uint32_t eep)
583 : : {
584 [ - + ]: 1 : NRFX_ASSERT(eep);
585 : 1 : *((volatile uint32_t *)(eep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
586 : 1 : }
587 : :
588 : 1 : __STATIC_INLINE void nrfx_gppi_task_endpoint_setup(uint8_t channel, uint32_t tep)
589 : : {
590 [ - + ]: 1 : NRFX_ASSERT(tep);
591 : 1 : *((volatile uint32_t *)(tep + 0x80uL)) = ((uint32_t)channel | DPPIC_SUBSCRIBE_CHG_EN_EN_Msk);
592 : 1 : }
593 : :
594 : 1 : __STATIC_INLINE void nrfx_gppi_channel_endpoints_setup(uint8_t channel,
595 : : uint32_t eep,
596 : : uint32_t tep)
597 : : {
598 : 1 : nrfx_gppi_event_endpoint_setup(channel, eep);
599 : 1 : nrfx_gppi_task_endpoint_setup(channel, tep);
600 : 1 : }
601 : :
602 : : __STATIC_INLINE void nrfx_gppi_event_endpoint_clear(uint8_t channel, uint32_t eep)
603 : : {
604 : : NRFX_ASSERT(eep);
605 : : (void)channel;
606 : : *((volatile uint32_t *)(eep + 0x80uL)) = 0;
607 : : }
608 : :
609 : : __STATIC_INLINE void nrfx_gppi_task_endpoint_clear(uint8_t channel, uint32_t tep)
610 : : {
611 : : NRFX_ASSERT(tep);
612 : : (void)channel;
613 : : *((volatile uint32_t *)(tep + 0x80uL)) = 0;
614 : : }
615 : :
616 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_setup(uint8_t channel, uint32_t fork_tep)
617 : : {
618 : : nrfx_gppi_task_endpoint_setup(channel, fork_tep);
619 : : }
620 : :
621 : : __STATIC_INLINE void nrfx_gppi_fork_endpoint_clear(uint8_t channel, uint32_t fork_tep)
622 : : {
623 : : nrfx_gppi_task_endpoint_clear(channel, fork_tep);
624 : : }
625 : :
626 : : __STATIC_INLINE void nrfx_gppi_channels_include_in_group(uint32_t channel_mask,
627 : : nrfx_gppi_channel_group_t channel_group)
628 : : {
629 : : nrf_dppi_channels_include_in_group(NRF_DPPIC,
630 : : channel_mask,
631 : : (nrf_dppi_channel_group_t)channel_group);
632 : : }
633 : :
634 : : __STATIC_INLINE void nrfx_gppi_channels_remove_from_group(uint32_t channel_mask,
635 : : nrfx_gppi_channel_group_t channel_group)
636 : : {
637 : : nrf_dppi_channels_remove_from_group(NRF_DPPIC,
638 : : channel_mask,
639 : : (nrf_dppi_channel_group_t)channel_group);
640 : : }
641 : :
642 : : __STATIC_INLINE void nrfx_gppi_group_clear(nrfx_gppi_channel_group_t channel_group)
643 : : {
644 : : nrf_dppi_group_clear(NRF_DPPIC, (nrf_dppi_channel_group_t)channel_group);
645 : : }
646 : :
647 : : __STATIC_INLINE void nrfx_gppi_group_enable(nrfx_gppi_channel_group_t channel_group)
648 : : {
649 : : nrf_dppi_group_enable(NRF_DPPIC, (nrf_dppi_channel_group_t)channel_group);
650 : : }
651 : :
652 : : __STATIC_INLINE void nrfx_gppi_group_disable(nrfx_gppi_channel_group_t channel_group)
653 : : {
654 : : nrf_dppi_group_disable(NRF_DPPIC, (nrf_dppi_channel_group_t)channel_group);
655 : : }
656 : :
657 : : __STATIC_INLINE uint32_t nrfx_gppi_task_address_get(nrfx_gppi_task_t gppi_task)
658 : : {
659 : : return nrf_dppi_task_address_get(NRF_DPPIC, (nrf_dppi_task_t)gppi_task);
660 : : }
661 : :
662 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_disable_task_get(nrfx_gppi_channel_group_t group)
663 : : {
664 : : return (nrfx_gppi_task_t) nrf_dppi_group_disable_task_get((uint8_t)group);
665 : : }
666 : :
667 : : __STATIC_INLINE nrfx_gppi_task_t nrfx_gppi_group_enable_task_get(nrfx_gppi_channel_group_t group)
668 : : {
669 : : return (nrfx_gppi_task_t) nrf_dppi_group_enable_task_get((uint8_t)group);
670 : : }
671 : :
672 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_alloc(uint8_t * p_channel)
673 : : {
674 : : #if NRFX_CHECK(NRFX_DPPI_ENABLED)
675 : : return nrfx_dppi_channel_alloc(p_channel);
676 : : #else
677 : : (void)p_channel;
678 : : return NRFX_ERROR_NOT_SUPPORTED;
679 : : #endif
680 : : }
681 : :
682 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_channel_free(uint8_t channel)
683 : : {
684 : : #if NRFX_CHECK(NRFX_DPPI_ENABLED)
685 : : return nrfx_dppi_channel_free(channel);
686 : : #else
687 : : (void)channel;
688 : : return NRFX_ERROR_NOT_SUPPORTED;
689 : : #endif
690 : : }
691 : :
692 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_alloc(nrfx_gppi_channel_group_t * p_group)
693 : : {
694 : : #if NRFX_CHECK(NRFX_DPPI_ENABLED)
695 : : return nrfx_dppi_group_alloc((nrf_dppi_channel_group_t *)p_group);
696 : : #else
697 : : (void)p_group;
698 : : return NRFX_ERROR_NOT_SUPPORTED;
699 : : #endif
700 : : }
701 : :
702 : : __STATIC_INLINE nrfx_err_t nrfx_gppi_group_free(nrfx_gppi_channel_group_t group)
703 : : {
704 : : #if NRFX_CHECK(NRFX_DPPI_ENABLED)
705 : : return nrfx_dppi_group_free((nrf_dppi_channel_group_t)group);
706 : : #else
707 : : (void)group;
708 : : return NRFX_ERROR_NOT_SUPPORTED;
709 : : #endif
710 : : }
711 : : #else
712 : : #error "Neither PPI nor DPPI is present in the SoC currently in use."
713 : : #endif
714 : :
715 : : #ifdef __cplusplus
716 : : }
717 : : #endif
718 : :
719 : : #endif // NRFX_GPPI_H
|