I have nrf5340 DK board with NrfConnectSDK with zephyr. I have built it using the Nrfxpwm driver because I want to get to all four channel in the first pmw instance. I have trouble sending the PWM signals out pins P0.23 and P0.22

[weightwatcherphil]

I started with the pwm_led example and merged some code from the SDK17 Pwm driver and it comiples and runs fine.  I have a 16 khz period and a 50% duty cycle and if I put it on pins

4,5,6,7  things work just fine.  but when i try to put it on p0.23 the processor starts rebooting.  I know P0.23 is a push button but I do not care about the button.  If i put the pwm output on P0.22 it goes from 3.0 to 1.3 volts.  it will not go to ground.  now on the nrf5340 DK board it says UART2  RX is using p0.22 .  I tried to disable uart2 in my .overlay file with

&uart2 {
status = "disabled";
};

but there was no change on p0.22.

Any help would be much appreciated.

thanks

phil

[weightwatcherphil]

just to make sure I follow this.  you found the device tree information in the file

C:\ncs\v2.4.0\zephyr\boards\arm\nrf5340dk_nrf5340\nrf5340_cpuapp_common-pinctrl.dtsi

/*
* Copyright (c) 2022 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/

&pinctrl {
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};

i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};

uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RTS, 0, 19)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_CTS, 0, 21)>;
bias-pull-up;
};
};

uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_RTS, 0, 19)>,
<NRF_PSEL(UART_CTS, 0, 21)>;
low-power-enable;
};
};

pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
};
};

pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
low-power-enable;
};
};

qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>,
<NRF_PSEL(QSPI_CSN, 0, 18)>;
nordic,drive-mode = <NRF_DRIVE_H0H1>;
};
};

qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>;
low-power-enable;
};
group2 {
psels = <NRF_PSEL(QSPI_CSN, 0, 18)>;
low-power-enable;
bias-pull-up;
};
};

uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 0)>;
bias-pull-up;
};
};

uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>,
<NRF_PSEL(UART_RX, 1, 0)>;
low-power-enable;
};
};

spi4_default: spi4_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};

spi4_sleep: spi4_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};

};