Guidelines for design to minimize ESD-caused resets of nRF51?

[ScottBBBB]

We're having difficulty preventing our nRF51822 from resetting when ESD events occur. These events are not directly on the nRF51's I/O pins, and we've tried things like grounding the SWDCLK and SWDIO lines, but to no avail. Compared to other MCUs, the part seems quite sensitive. Are there guidelines available which can help us benefit from the experiences of others in this area?

Thanks, Scott

[ScottBBBB]

So it sounds like it's difficult to prevent a reset from occurring, given how short a pulse is sufficient to cause it. We will have to take a number of measures simultaneously, from the sound of it. Thanks, Scott

[ovrebekk]

A reset could happen quite easily if you are exposed to a strong ESD event, that is true. I would try adding the cap and/or pull up as described above and see if it solves the issue.