When the input voltage of lpcom is higher than VDD

Question

HI 
 I'm trying to use lpcom to detect when the battery voltage is dropping. 
 
 The configuration is as follows: 5V battery voltage output is reduced to 3.0V through LDO and supplied to nRF52832. 
 * Battery voltage = 5 .0V --- > LDO output = 3.0V -----> nRF52832 
 * The battery voltage is divided by a resistance of approximately 2M or more and input to the lpcom port. 
 
 There were no problems with the basic implementation in operation tests and continuous tests for about a month. 
 
 But when I looked again, 
 When the battery is fully charged... the VDD voltage of nRF52 is set high by about 0.9V. 
 Could this part be a problem? 
 
 There is no problem in operation, but will there be a problem in the long run if a voltage higher than the guaranteed voltage is applied?

Simonr · Accepted Answer

Hi 
 David_Kim said: If a voltage higher than the above VDD is applied, can there be a problem with durability, etc.? 
 Yes, since the behavior is unspecified we haven't tested for what might happen, so this can be a problem and this should be avoided since what will happen is not specified. You should add some kind of logic or component that ensures the input voltage on LPCOMP doesn't exceed 3.3V. 
 Note that since what will happen is unspecified, we can't guarantee that something will happen either, but you're operating the device outside of the product specification, so we can't tell what will or will not happen if you keep running it like this. We can only recommend that you don't. 
 Best regards, 
 Simon

When the input voltage of lpcom is higher than VDD

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