Nrf52 flash programming : 'writes in a block between erase'

[Mahendra Tailor]

In the nrf52 OPS datasheet, for NVM and flash programming electrical specification (page 41) it has "Amount of writes in a block between erase" and Minimum for that is 181.

What does that actually mean?

For example, I know and understand "Write/erase cycles", but this is a new one on me.

A sector in nrf52 has 4K which means 1024 dwords. Which means I could end up having 1024 write operations before it is full. So the 181 specified can't be referring to how many times I could write.

To make matters worse, there are 32 bits in a write operation, so there are 32768 bits. So I could theretically have 32 seperate write operations at each of the 1024 locations, giving me a total of 32768 write operation before I would have to erase the block.

I am confused !!

Hope someone can clarify.

[Mahendra Tailor]

I asked and the definitive answer about how many times one can write to a dword is as per the following response I got ...

The real limitation is that you can write up to 8 times to the same address, as long as you don't touch other 32-bit words inside the same 128-bit block. For simplicity we have stated in the product specification that the maximum is 2 writes for a 32-bit word. The limitation should be considered hard as breaking it may result in bits being flipped.

So I asked a follow on question about the address boundary of that 128 bit block and the answer was ...

I can confirm that the start addresses of the 128 bit blocks are those addresses which are divisible by 16.

I think I can manage to develop I driver to atomically write a multidword object and still be able to detect an interruption on next power up.