Try to program a custom board using BL5340PA module to see LOG

[D.MASSIALA]

I have made a PCB using a BL5340PA module, to start i have tried a simple code to see log from RTT using the SWD SWCLK pin, i am using an NRF5340 DK as debugger/programmer, my pin connection bewteen my board  and nrf5340 dk seem good as i was able to flash the code without error.

But still can't see the log in JLink RTT Viewer.

#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>


LOG_MODULE_REGISTER(main, LOG_LEVEL_DBG);


int main(void)
{
        LOG_INF("Hello from RTT!");
        while (1) {
                LOG_DBG("Toggling");
                 k_msleep(1000);
         }
        return 0;
}

[D.MASSIALA]

I have create my board's DTS file but i don't know what to put inside.

/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "custom_bl5340pa-pinctrl.dtsi"

/ {
	model = "Custom Board auto generated by nRF Connect for VS Code (CPUAPP)";
	compatible = "Ezurio,custom-bl5340pa-cpuapp";

	chosen {
		zephyr,sram = &sram0_image;
		zephyr,flash = &flash0;
		zephyr,code-partition = &slot0_partition;
		zephyr,sram-secure-partition = &sram0_s;
		zephyr,sram-non-secure-partition = &sram0_ns;
	};
};

#include "custom_bl5340pa-cpuapp_partitioning.dtsi"
#include "custom_bl5340pa-shared_sram.dtsi"

[D.MASSIALA]

When i try to debug, i still block in line 131 of the cpu_idle.c, what that means ? 

/*
 * Copyright (c) 2013-2014 Wind River Systems, Inc.
 * Copyright (c) 2023 Arm Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/**
 * @file
 * @brief ARM Cortex-M power management
 */
#include <zephyr/kernel.h>
#include <cmsis_core.h>

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#include <soc_cpu_idle.h>
#endif

/**
 * @brief Initialization of CPU idle
 *
 * Only called by arch_kernel_init(). Sets SEVONPEND bit once for the system's
 * duration.
 */
void z_arm_cpu_idle_init(void)
{
	SCB->SCR = SCB_SCR_SEVONPEND_Msk;
}

#if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
#define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
#else
#define ON_EXIT_IDLE_HOOK do {} while (false)
#endif

#if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
#define SLEEP_IF_ALLOWED(wait_instr) do { \
	/* Skip the wait instr if on_enter_cpu_idle returns false */ \
	if (z_arm_on_enter_cpu_idle()) { \
		/* Wait for all memory transaction to complete */ \
		/* before entering low power state. */ \
		__DSB(); \
		wait_instr(); \
		/* Inline the macro provided by SoC-specific code */ \
		ON_EXIT_IDLE_HOOK; \
	} \
} while (false)
#else
#define SLEEP_IF_ALLOWED(wait_instr) do { \
	__DSB(); \
	wait_instr(); \
	ON_EXIT_IDLE_HOOK; \
} while (false)
#endif

void arch_cpu_idle(void)
{
#if defined(CONFIG_TRACING)
	sys_trace_idle();
#endif

#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
	z_arm_on_enter_cpu_idle_prepare();
#endif

#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/*
	 * PRIMASK is always cleared on ARMv7-M and ARMv8-M (not used
	 * for interrupt locking), and configuring BASEPRI to the lowest
	 * priority to ensure wake-up will cause interrupts to be serviced
	 * before entering low power state.
	 *
	 * Set PRIMASK before configuring BASEPRI to prevent interruption
	 * before wake-up.
	 */
	__disable_irq();

	/*
	 * Set wake-up interrupt priority to the lowest and synchronize to
	 * ensure that this is visible to the WFI instruction.
	 */
	__set_BASEPRI(0);
	__ISB();
#else
	/*
	 * For all the other ARM architectures that do not implement BASEPRI,
	 * PRIMASK is used as the interrupt locking mechanism, and it is not
	 * necessary to set PRIMASK here, as PRIMASK would have already been
	 * set by the caller as part of interrupt locking if necessary
	 * (i.e. if the caller sets _kernel.idle).
	 */
#endif

	SLEEP_IF_ALLOWED(__WFI);

	__enable_irq();
	__ISB();
}

void arch_cpu_atomic_idle(unsigned int key)
{
#if defined(CONFIG_TRACING)
	sys_trace_idle();
#endif

#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
	z_arm_on_enter_cpu_idle_prepare();
#endif

	/*
	 * Lock PRIMASK while sleeping: wfe will still get interrupted by
	 * incoming interrupts but the CPU will not service them right away.
	 */
	__disable_irq();

	/*
	 * No need to set SEVONPEND, it's set once in z_arm_cpu_idle_init()
	 * and never touched again.
	 */

#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
	/* No BASEPRI, call wfe directly. (SEVONPEND is set in z_arm_cpu_idle_init()) */
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	/* unlock BASEPRI so wfe gets interrupted by incoming interrupts  */
	__set_BASEPRI(0);
	__ISB();
#else
#error Unsupported architecture
#endif

	SLEEP_IF_ALLOWED(__WFE);

	arch_irq_unlock(key);
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
	__enable_irq();
#endif
}

[D.MASSIALA]

resolve need to add in prj.conf 

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

CONFIG_CLOCK_CONTROL_NRF_K32SRC_500PPM=y