Problem with BLE DFU

[phlb]

Hello!

I have a problem with ble DFU application upgrade. I use the Master Control Panel 3.10.0.14 under Win 7 on virtual machine and nordic ble usb dongle. On the firmware Soft Device S110 8.0.0, a boot loader dfu dual bank based on the example in SDK 9.0.0.

My application use the SDK 10.0.0 and it switch in bootloader/DFU mode. The communication is established and data packet transmission begin correctly but often the master control stop the communication on an acknowledgement timeout.

Did you have any feedbacks from other users with a similar issues and eventually a fix?

Regards,

[phlb]

I use HEX file generated by IAR with my application project (based on Nordic HRS example). It's the same behavior with original Nordic HRS HEX file.

Sometimes upgrade process is done without any problem, and sometimes I retry several times the upgrade process failed at 20%, 60%... .

In bootloader I modified the main.c. I removed led and button code management for the Nordic Development Board.

I flashed the application, bootloader and soft device with the nrfGoStudio.

Another detail, I use a nrf51822 AC.

I don't have a sniffer hardware and software at this day.

I modified the ICF file for linker.

/###ICF### Section handled by ICF editor, don't touch! / /-Editor annotation file-/ / IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" / /-Specials-/ define symbol ICFEDIT_intvec_start = 0x3c000; /-Memory Regions-/ define symbol ICFEDIT_region_ROM_start = 0x3c000; define symbol ICFEDIT_region_ROM_end = 0x3fbff; define symbol ICFEDIT_region_RAM_start = 0x20002c00; define symbol ICFEDIT_region_RAM_end = 0x20007f7f; /-Sizes-/ define symbol ICFEDIT_size_cstack = 0x800; define symbol ICFEDIT_size_heap = 0x200; /*** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G; define region ROM_region = mem:[from ICFEDIT_region_ROM_start to ICFEDIT_region_ROM_end]; define region RAM_region = mem:[from ICFEDIT_region_RAM_start to ICFEDIT_region_RAM_end];

define block CSTACK with alignment = 8, size = ICFEDIT_size_cstack { }; define block HEAP with alignment = 8, size = ICFEDIT_size_heap { };

initialize by copy { readwrite }; do not initialize { section .noinit };

keep { section .intvec }; place at address mem:ICFEDIT_intvec_start { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, block CSTACK, block HEAP };