Help finding documentation for PK.COMMAND.OPEADDR on nRF54L15

[William Pereira]

Hello everyone,

I’m currently working on implementing the PK peripheral using Rust with the SVD files for the nRF54L15, but I’m running into a documentation issue.

In the nRF54L15 documentation, there’s a field named OPEADDR under PK.COMMAND, and the description says “See documentation for more details.” However, I haven’t been able to locate any additional documentation or reference that explains this field further.

Does anyone know where I can find this missing documentation or any related reference for the OPEADDR field?

Thanks in advance for any help or pointers.

[Einar Thorsrud]

Hi,

I suspect that the OPEADDR field documentation is there by a mistake and that it can be ignored. But I am checking internally and will update here when I know more.

[William Pereira]

Thanks for the clarification.

If the `OPEADDR` field can be ignored, what should be used in its place? I’m trying to implement ECC and HASH operations using the SVD, but it feels like some parts of the documentation are missing.

Do you happen to have any example code (in C or another language) that performs HASH or ECC operations using the CRACEN peripheral? That would be very helpful.

Thanks again for checking internally.

[Einar Thorsrud]

Hi,

I suspect you can just leave OPEADDR at the reset value (it may take a bit of time before I can say more about this field). Regarding samples, the SDK contain several crypto samples and the driver is available in source code so you can step down into it and see what it does.

[William Pereira]

Hello Einar, still trying to figure this part. 


Let me explain what I did:

I am trying to implement a P-256 scalar multiplication directly through CRACEN’s PK registers (without PSA or the Silex wrappers). I would like confirmation that I am configuring the PK engine correctly. ( I am using your ECDH example as base)

Here is the sequence I follow:

1. Enable CRACEN: RNG, CRYPTOMASTER, and PKEIKG.

2. Wait until both PK and IKG report “not busy”.

3. Configure PK.COMMAND with:

   • OPEADDR = 0x22 (ECC point multiplication)

   • OPBYTESM1 = 31 (32-byte operands)

   • SELCURVE = P256

   • SWAPBYTES = 1 (to match operand endianness on the example)

4. Write the operands into CRACEN RAM, everything is 32 bytes big endian:

   • Slot 12 (address 0x518099e0)  contains the X coordinate of the peer public key. (and  slot 13 (0x51809be0) contains the Y coord)

   • Slot 8 (0x518091e0) contains the private scalar.

   • Slot C is reserved for the result.

5. Configure PK.POINTERS so that:

   • Pointer A points to 12,

   • Pointer B points to 8,

   • Pointer C points to 10. everything exactly like the example.

6. Start the operation using PK.CONTROL with START=1 and clear previous IRQ.

Despite following this sequence, the engine reports errorflags = 1 << 4 (“point not on curve”) even when using a known valid P-256 public key.

Question:
Is there any additional register, sequencing requirement, memory alignment detail, or PK RAM layout rule enforced by CRACEN for ECC multiplication that is not explicitly documented? I want to confirm whether my register configuration is complete, or if there is a hidden constraint similar to those used inside the PSA/Silex driver.

Here is the code:
github.com/.../ecdh.rs

[Emil Lenngren]

Did you write the microcode first?
See the note under https://docs.nordicsemi.com/bundle/ncs-3.1.1/page/nrf/app_dev/device_guides/nrf54l/cryptography.html#kmu_and_cracen_peripherals.

Driver code: https://github.com/nrfconnect/sdk-nrf/blob/d0af91f7f356961b3de59e16d0c9e4c2bfdd61bb/subsys/nrf_security/src/drivers/cracen/cracenpsa/src/cracen.c#L41.