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  • Case ID: 356336
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mcuboot + spi ext flash + overwrite + tfm fails to jump to application

ioabro

Hi!

NCS 3.1 On a custom board with nrf5340 and nrf7002, have successfully implemented and tested FOTA over Bluetooth Low Energy with Simultaneous updates for both cores of the nRF5340 with external SPI flash built without TF-M and now trying to accomplish it with TF-M but it fails to boot the application. 

proj-ns.conf

CONFIG_RESET_ON_FATAL_ERROR=n
CONFIG_REBOOT=y

CONFIG_USE_SEGGER_RTT=y

CONFIG_LOG=y
CONFIG_LOG_BACKEND_RTT=y
CONFIG_LOG_BACKEND_UART=n

# Make RTT the console device
CONFIG_RTT_CONSOLE=y
CONFIG_UART_CONSOLE=n

CONFIG_FPU=y
CONFIG_FPU_SHARING=y

CONFIG_MAIN_STACK_SIZE=4096
# Some command handlers require a large stack.
CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2560

# Enable Kconfigs for SPI and GPIO
CONFIG_GPIO=y
CONFIG_SPI=y

CONFIG_HEAP_MEM_POOL_SIZE=16384

CONFIG_NEWLIB_LIBC=y
CONFIG_NEWLIB_LIBC_FLOAT_PRINTF=y

# External Flash
CONFIG_FLASH=y
CONFIG_FLASH_JESD216_API=y

# Deprecated NFC configuration - moved to overlay file
CONFIG_NFCT_PINS_AS_GPIOS=y

# Ensure an MCUboot-compatible binary is generated.
CONFIG_BOOTLOADER_MCUBOOT=y

CONFIG_MCUBOOT_UTIL_LOG_LEVEL_DBG=y
# Enable mcumgr DFU in application
CONFIG_MCUMGR=y

# Enable MCUMGR management for both OS and Images
CONFIG_MCUMGR_GRP_OS=y
CONFIG_MCUMGR_GRP_IMG=y

# Enable bootloader info group to report mcuboot version
CONFIG_MCUMGR_GRP_OS_BOOTLOADER_INFO=y

# Dependencies
# Configure dependencies for CONFIG_MCUMGR  
CONFIG_NET_BUF=y
CONFIG_ZCBOR=y
CONFIG_CRC=y

# Configure dependencies for CONFIG_MCUMGR_GRP_IMG  
# CONFIG_FLASH=y
CONFIG_IMG_MANAGER=y

# Configure dependencies for CONFIG_IMG_MANAGER  
CONFIG_STREAM_FLASH=y
CONFIG_FLASH_MAP=y

# Not sure if needed, but included to be safe
CONFIG_BASE64=y
CONFIG_CRC=y

# Enable SPI driver for the application
CONFIG_SPI_NOR=y
CONFIG_SPI_NOR_SFDP_DEVICETREE=y
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096

# STAT Configs below only usefull for debugging
# Required by the `taskstat` command.
CONFIG_THREAD_MONITOR=y

# Support for taskstat command
CONFIG_MCUMGR_GRP_OS_TASKSTAT=y

# Enable statistics and statistic names.
CONFIG_STATS=y
CONFIG_STATS_NAMES=y

CONFIG_MCUMGR_GRP_STAT=y

Kconfig

source "Kconfig.zephyr"

menu "Nordic BLE GATT service sample"

config BT_SECURITY_ENABLED
	bool "Enable security"
	default y
	select BT_SMP
	select BT_SETTINGS
	select FLASH
	select FLASH_PAGE_LAYOUT
	select FLASH_MAP
	select ZMS if (SOC_FLASH_NRF_RRAM || SOC_FLASH_NRF_MRAM)
	select NVS if !(SOC_FLASH_NRF_RRAM || SOC_FLASH_NRF_MRAM)
	select SETTINGS
	help
	  "Enable BLE security features."

endmenu

Kconifg.sysbuild

source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"

config NRF_DEFAULT_IPC_RADIO
	default y

config NETCORE_IPC_RADIO_BT_HCI_IPC
	default y

overlay-bt.conf

CONFIG_BT=y
CONFIG_BT_PERIPHERAL=y

CONFIG_BT_SMP=y
# CONFIG_BT_SMP_SC_ONLY=y

# Allow for large Bluetooth data packets.
CONFIG_BT_L2CAP_TX_MTU=498
CONFIG_BT_BUF_ACL_RX_SIZE=502
CONFIG_BT_BUF_ACL_TX_SIZE=502
CONFIG_BT_CTLR_DATA_LENGTH_MAX=251
# CONFIG_NCS_SAMPLE_MCUMGR_BT_OTA_DFU_SPEEDUP=y

# Enable the Bluetooth mcumgr transport (unauthenticated).
CONFIG_MCUMGR_TRANSPORT_BT=y
CONFIG_MCUMGR_TRANSPORT_BT_CONN_PARAM_CONTROL=y

# Enable the Shell mcumgr transport.
CONFIG_SHELL=n
CONFIG_SHELL_BACKEND_SERIAL=n
CONFIG_MCUMGR_TRANSPORT_SHELL=n

# Enable the mcumgr Packet Reassembly feature over Bluetooth and its configuration dependencies.
# MCUmgr buffer size is optimized to fit one SMP packet divided into five Bluetooth Write Commands,
# transmitted with the maximum possible MTU value: 498 bytes.
CONFIG_MCUMGR_TRANSPORT_BT_REASSEMBLY=y
CONFIG_MCUMGR_TRANSPORT_NETBUF_SIZE=2475
CONFIG_MCUMGR_GRP_OS_MCUMGR_PARAMS=y
CONFIG_MCUMGR_TRANSPORT_WORKQUEUE_STACK_SIZE=4608

# Enable the LittleFS file system.
CONFIG_FILE_SYSTEM=y
CONFIG_FILE_SYSTEM_LITTLEFS=y

# Enable file system commands
CONFIG_MCUMGR_GRP_FS=y

# Enable the storage erase command.
CONFIG_MCUMGR_GRP_ZBASIC=y
CONFIG_MCUMGR_GRP_ZBASIC_STORAGE_ERASE=y

# Disable Bluetooth ping support
CONFIG_BT_CTLR_LE_PING=n

# Disable shell commands that are not needed
CONFIG_CLOCK_CONTROL_NRF_SHELL=n
CONFIG_DEVICE_SHELL=n
CONFIG_DEVMEM_SHELL=n
CONFIG_FLASH_SHELL=n

# Enable Bluetooth security features
CONFIG_BT_SECURITY_ENABLED=y

# Permission levels for GATT characteristics of the SMP service.
# CONFIG_MCUMGR_TRANSPORT_BT_PERM_RW_AUTHEN=y
# CONFIG_MCUMGR_TRANSPORT_BT_PERM_RW_ENCRYPT=y
CONFIG_MCUMGR_TRANSPORT_BT_PERM_RW=y

# Dynamic SMP service registration
# CONFIG_MCUMGR_TRANSPORT_BT_DYNAMIC_SVC_REGISTRATION=y

sysbuild/ipc_radio.conf

CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_LOG=y

sysbuild/mcuboot.conf

# Enable logging for MCUboot
CONFIG_LOG=y
CONFIG_LOG_MODE_MINIMAL=n
CONFIG_MCUBOOT_LOG_LEVEL_DBG=y

CONFIG_USE_SEGGER_RTT=y
CONFIG_RTT_CONSOLE=y
CONFIG_UART_CONSOLE=n
CONFIG_LOG_BACKEND_RTT=y
CONFIG_LOG_BACKEND_UART=n

# If UART
# CONFIG_MCUBOOT_SERIAL=y
# CONFIG_BOOT_SERIAL_UART=y
# Turn on a LED so we can see when Serial Recovery mode is active
# CONFIG_MCUBOOT_INDICATION_LED=n

# Enable SPI driver for MCUboot
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_NOR=y
CONFIG_SPI_NOR_SFDP_DEVICETREE=y
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
CONFIG_FLASH=y
# QSPI drivers are enabled by default for some chips.
# Disable it explicitly to be sure QSPI is disabled.
CONFIG_NORDIC_QSPI_NOR=n 

# required by SPI driver
CONFIG_MULTITHREADING=y

# Increase number of sectors
CONFIG_BOOT_MAX_IMG_SECTORS=256

# 0xF000 is chosen somewhat arbitrarily,
# so remember to optimize this size in your own project
CONFIG_PM_PARTITION_SIZE_MCUBOOT=0xF000


# # MCUBoot and Partition Manager
CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
# CONFIG_PM_PARTITION_SIZE_MCUBOOT=0x10000
# CONFIG_BOOT_MAX_IMG_SECTORS=256
CONFIG_BOOT_ERASE_PROGRESSIVELY=y
CONFIG_SOC_FLASH_NRF_EMULATE_ONE_BYTE_WRITE_ACCESS=y

# # Use minimal C library instead of the Picolib
# CONFIG_MINIMAL_LIBC=y

 

sysbuild/mcuboot.overlay

/ {
	chosen {
		nordic,pm-ext-flash = &is25lp128f;
	};

	buttons {
		compatible = "gpio-keys";

		button0: button_0 {
			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
			label = "nFactory Reset";
			zephyr,code = <INPUT_KEY_0>;
		};
	};

	aliases {
		mcuboot-button0 = &button0; // if needed
	};
};


&spi4 {
	status = "okay";
	cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;

	/delete-node/ mx25r6435f@0;

	// JEDEC JESD216
	is25lp128f: is25lp128f@0 {
		compatible = "issi,is25lp128f", "jedec,spi-nor";
		/* reg is the chip select number here */
		reg = <0>;
		spi-max-frequency = <DT_FREQ_M(32)>; // 133 MHz (can also be 166 MHz)
		// wp-gpios = <&gpio0 GPIO_ACTIVE_LOW>;
		// hold-gpios = <&gpio0 GPIO_ACTIVE_LOW>;
		reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; // MEM_nRESET It has an internal pull-up resistor and may be left floating if not used.
		jedec-id = [ 9d 60 18  ]; // Manufacturer ID 9D, Device ID 17
		size = <134217728>; // 128 Mbit = 16 MByte
		sfdp-bfp = [ e5 20 fb ff ff ff ff 07 44 eb 08 6b 08 3b 80 bb fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 10 d8 00 ff 62 42 a9 00 82 d8 01 c8 ec 8d 69 4c 7a 75 7a 75 f7 a2 d5 5c 4a c2 2c ff e1 30 fa a9  ];
		quad-enable-requirements = "NONE";
		enter-4byte-addr = <0>;
		page-size = <256>;
	};
};

// &gpio_fwd {
// 	status = "okay";

// 	uart {
// 		gpios = <&gpio1 12 0>, <&gpio1 10 0>;
// 	};
// };

&uart0 {
	// status = "okay"; // Adjust if uart0 is required
	status = "disabled";
};


&pinctrl {
	spi4_default: spi4_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
			        <NRF_PSEL(SPIM_MISO, 0, 10)>,
			        <NRF_PSEL(SPIM_MOSI, 0, 9)>;
		};
	};

	spi4_sleep: spi4_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
			        <NRF_PSEL(SPIM_MISO, 0, 10)>,
			        <NRF_PSEL(SPIM_MOSI, 0, 9)>;
			low-power-enable;
		};
	};

	// Uncomment lines below if uart0 is required
	// uart0_default: uart0_default {
	// 	group1 {
	// 		psels = <NRF_PSEL(UART_TX, 0, 20)>;
	// 	};

	// 	group2 {
	// 		psels = <NRF_PSEL(UART_RX, 0, 22)>;
	// 		bias-pull-up;
	// 	};
	// };

	// uart0_sleep: uart0_sleep {
	// 	group1 {
	// 		psels = <NRF_PSEL(UART_TX, 0, 20)>,
	// 				<NRF_PSEL(UART_RX, 0, 22)>;
	// 		low-power-enable;
	// 	};
	// };
};

&spi3 {
	status = "disabled";
};

&spi2 {
	status = "disabled";
};

&spi1 {
	status = "disabled";
};

&spi0 {
	status = "disabled";
};

&i2c0 {
	status = "disabled";
};

&i2c1 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&uart1 {
	status = "disabled";
};

&uart2 {
	status = "disabled";
};

&uart3 {
	status = "disabled";
};

&nfct {
	status = "disabled";
};

// When enabled this property will configure pins dedicated to NFCT peripheral as regular GPIOs.
// NFC pins in nRF52 series: P0.09 and P0.10 NFC pins in nRF5340: P0.02 and P0.03
// This setting, once applied, can only be unset by erasing the UICR registers. 
// Refer to the reference manual for more details.
&uicr {
	nfct-pins-as-gpios;
};

sysbuild.conf

# MCUboot
SB_CONFIG_BOOTLOADER_MCUBOOT=y

# Add private key for MCUboot
SB_CONFIG_BOOT_SIGNATURE_KEY_FILE="C:......private_key.pem"
# Configure key type
SB_CONFIG_BOOT_SIGNATURE_TYPE_ECDSA_P256=y

# Needed for FOTA for nRF5340 and TF-M
SB_CONFIG_MCUBOOT_USE_ALL_AVAILABLE_RAM=y

# MCUboot should use external flash
SB_CONFIG_PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY=y
# For SPI, we need to set this
SB_CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y

# Add b0n image - Enables nRF Secure Immutable Bootloader for the network core
SB_CONFIG_SECURE_BOOT_NETCORE=y

# Add private key for network core bootloader (b0n).
SB_CONFIG_SECURE_BOOT_SIGNING_KEY_FILE="C:/......private_key.pem"

# Set up multiple partitions
SB_CONFIG_MCUBOOT_UPDATEABLE_IMAGES=2
# Add support to netcore for DFU
SB_CONFIG_NETCORE_APP_UPDATE=y
# Add support to mcuboot for updating two cores simultaneously
SB_CONFIG_MCUBOOT_NRF53_MULTI_IMAGE_UPDATE=y
# Simultaneous FOTA does not support rollback
SB_CONFIG_MCUBOOT_MODE_OVERWRITE_ONLY=y

# SB_CONFIG_NETCORE_IPC_RADIO only works for multi-core chips
# For single core chips, use
# Kconfig.sysbuild (works for both single-core and multi-core chips)
# Enable IPC Radio for the network core
# SB_CONFIG_NETCORE_IPC_RADIO=y
# Configure protocol for IPC Radio
# SB_CONFIG_NETCORE_IPC_RADIO_BT_HCI_IPC=y

boards\nrf7002dk_nrf5340_cpuapp_ns.overlay

/ {
	chosen {
		nordic,pm-ext-flash = &is25lp128f;
	};


};

&rtc0 {
	status = "okay";
	clock-frequency = <32768>;
	prescaler = <1>;
};


&spi4 {
	status = "okay";
	cs-gpios = <&gpio0 03 GPIO_ACTIVE_LOW>,
			   <&gpio0 27 GPIO_ACTIVE_LOW>;

	/delete-node/ mx25r6435f@0;

	something here

	// JEDEC JESD216
	is25lp128f: is25lp128f@1 {
		compatible = "issi,is25lp128f", "jedec,spi-nor";
		/* reg is the chip select number here */
		reg = <1>;
		spi-max-frequency = <DT_FREQ_M(32)>; // 133 MHz (can also be 166 MHz)
		// wp-gpios = <&gpio0 GPIO_ACTIVE_LOW>;
		// hold-gpios = <&gpio0 GPIO_ACTIVE_LOW>;
		reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; // MEM_nRESET It has an internal pull-up resistor and may be left floating if not used.
		jedec-id = [ 9d 60 18  ]; // Manufacturer ID 9D, Device ID 17
		size = <134217728>; // 128 Mbit = 16 MByte
		sfdp-bfp = [ e5 20 fb ff ff ff ff 07 44 eb 08 6b 08 3b 80 bb fe ff ff ff ff ff 00 ff ff ff 44 eb 0c 20 0f 52 10 d8 00 ff 62 42 a9 00 82 d8 01 c8 ec 8d 69 4c 7a 75 7a 75 f7 a2 d5 5c 4a c2 2c ff e1 30 fa a9  ];
		quad-enable-requirements = "NONE";
		enter-4byte-addr = <0>;
		page-size = <256>;
	};
};

&spi2 {
	status = "disabled";
};

&spi1 {
	status = "disabled";
};

&spi0 {
	status = "disabled";
};

&uart1 {
	status = "disabled";
};

&uart3 {
	status = "disabled";
};

&usbd {
	status = "disabled";
};

&i2c0 {
	status = "disabled";
};

&i2c2 {
	status = "disabled";
};

&i2c3 {
	status = "disabled";
};

&pinctrl {
	spi4_default: spi4_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
			        <NRF_PSEL(SPIM_MISO, 0, 10)>,
			        <NRF_PSEL(SPIM_MOSI, 0, 9)>;
		};
	};

	spi4_sleep: spi4_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
			        <NRF_PSEL(SPIM_MISO, 0, 10)>,
			        <NRF_PSEL(SPIM_MOSI, 0, 9)>;
			low-power-enable;
		};
	};
};

&nfct {
	status = "disabled";
};

After building and flashing the ns variant the bootloader keeps rebooting and the rtt log is:

*** Booting MCUboot v2.1.0-dev-2b69d93e75bc ***
*** Using nRF Connect SDK v3.1.0-6c6e5b32496e ***
*** Using Zephyr OS v4.1.99-1612683d4010 ***
I: Starting bootloader
D: context_boot_go
I: Image index: 0, Swap type: none
I: Image index: 1, Swap type: none
D: boot_validate_slot: slot 0, expected_swap_type 0
D: bootutil_img_validate: flash area 0xaae4
D: bootutil_img_hash
D: bootutil_tlv_iter_begin: type 65535, prot == 0
D: bootutil_img_validate: TLV off 253408, end 253740
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253408 ending at 253740
D: bootutil_tlv_iter_next: TLV 16 found at 253412 (size 32)
D: bootutil_img_validate: EXPECTED_HASH_TLV == 16
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253444 ending at 253740
D: bootutil_tlv_iter_next: TLV 1 found at 253448 (size 32)
D: bootutil_img_validate: EXPECTED_KEY_TLV == 1
D: bootutil_find_key
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253480 ending at 253740
D: bootutil_tlv_*** Booting MCUboot v2.1.0-dev-2b69d93e75bc ***
*** Using nRF Connect SDK v3.1.0-6c6e5b32496e ***
*** Using Zephyr OS v4.1.99-1612683d4010 ***
I: Starting bootloader
D: context_boot_go
I: Image index: 0, Swap type: none
I: Image index: 1, Swap type: none
D: boot_validate_slot: slot 0, expected_swap_type 0
D: bootutil_img_validate: flash area 0xaae4
D: bootutil_img_hash
D: bootutil_tlv_iter_begin: type 65535, prot == 0
D: bootutil_img_validate: TLV off 253408, end 253740
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253408 ending at 253740
D: bootutil_tlv_iter_next: TLV 16 found at 253412 (size 32)
D: bootutil_img_validate: EXPECTED_HASH_TLV == 16
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253444 ending at 253740
D: bootutil_tlv_iter_next: TLV 1 found at 253448 (size 32)
D: bootutil_img_validate: EXPECTED_KEY_TLV == 1
D: bootutil_find_key
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253480 ending at 253740
D: bootutil_tlv_

trying to debug the rtt log is this repeated message:

D: boot_validate_slot: slot 0, expected_swap_type 0
D: Left boot_go with success == 1
I: Bootloader chainload address offset: 0x10000
I: Image version: v1.2.3
I: Jumping to the first image slot
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253555 ending at 253555
D: bootutil_tlv_iter_next: TLV 65535 not found
D: boot_validate_slot: slot 0, expected_swap_type 0
D: Left boot_go with success == 1
I: Bootloader chainload address offset: 0x10000
I: Image version: v1.2.3
I: Jumping to the first image slot
D: bootutil_tlv_iter_next: searching for 65535 (65535 is any) starting at 253555 ending at 253555
D: bootutil_tlv_iter_next: TLV 65535 not found
D: boot_validate_slot: slot 0, expected_swap_type 0
D: Left boot_go with success == 1
I: Bootloader chainload address offset: 0x10000
I: Image version: v1.2.3
I: Jumping to the first image slot

Why is this behavior? Which configuration is missing or wrong when building with TF-M?

  • 0 in reply to Håkon Alseth

    Hi Håkon,

    I have a nrf7002dk and i just tested Simultaneous updates for both cores of the nRF5340 for SPI with board nrf7002dk/nrf5340/cpuapp/ns

    I modified

    mcuboot.conf

    # Step 6.2 - MCUboot should use external flash
CONFIG_NORDIC_QSPI_NOR=n
CONFIG_BOOT_MAX_IMG_SECTORS=256

# Step 1.2 - Enable SPI driver for MCUboot
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_NOR=y
CONFIG_SPI_NOR_SFDP_DEVICETREE=y
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
# QSPI drivers are enabled by defualt for some chips.
# Disable it explicitly to be sure QSPI is disabled.
CONFIG_NORDIC_QSPI_NOR=n 

# required by SPI driver
CONFIG_MULTITHREADING=y

    and 

    sysbuild.conf

    SB_CONFIG_BOOTLOADER_MCUBOOT=y
SB_CONFIG_MCUBOOT_USE_ALL_AVAILABLE_RAM=y

# Step 6.3 - Configure project to use external flash for DFU
SB_CONFIG_PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY=y
# Step 3.1 - For SPI, we need to set  this
SB_CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y

# Step 7.2 - Add b0n image
SB_CONFIG_SECURE_BOOT_NETCORE=y

# Step 7.3 - Set up multiple partitions
SB_CONFIG_MCUBOOT_UPDATEABLE_IMAGES=2

# Step 7.4 - Add support to netcore for DFU
SB_CONFIG_NETCORE_APP_UPDATE=y

# Step 7.5 - Add support to mcuboot for updating
# two cores simultaneously
SB_CONFIG_MCUBOOT_NRF53_MULTI_IMAGE_UPDATE=y

# Step 7.6 - Simultaneous FOTA does not support rollback
SB_CONFIG_MCUBOOT_MODE_OVERWRITE_ONLY=y

    rest are exact same as in the example.

    I am getting the same error. Cannot jump to the first image slot.

    Thank you.

  • 0 in reply to ioabro

    Sorry, you are right. Look at this one, and check the SPI related configurations, ie. sysbuild.conf and sysbuild/ folder here:

    Håkon Alseth said:
    L9_e3_sol (https://github.com/NordicDeveloperAcademy/ncs-inter/tree/main/l9/l9_e3_sol/spi)

    And combine this into your current project.

     

    Kind regards,

    Håkon

  • 0 in reply to Håkon Alseth

    Hej Håkon,

    It doesn't work.

    proj.conf

    #
# Copyright (c) 2018 Nordic Semiconductor
#
# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
#
CONFIG_NCS_SAMPLES_DEFAULTS=y

CONFIG_BT=y
CONFIG_BT_PERIPHERAL=y
CONFIG_BT_DEVICE_NAME="Nordic_LBS3"

# Enable the LBS service
CONFIG_BT_LBS=y
CONFIG_BT_LBS_POLL_BUTTON=y
CONFIG_DK_LIBRARY=y

CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048

# Step 2.2 - Enable FOTA over Bluetooth LE
CONFIG_NCS_SAMPLE_MCUMGR_BT_OTA_DFU=y


CONFIG_GPIO=y

# Enable mcumgr DFU in application
CONFIG_MCUMGR=y

# Enable MCUMGR management for both OS and Images
CONFIG_MCUMGR_GRP_OS=y
CONFIG_MCUMGR_GRP_IMG=y

# Configure MCUMGR transport to UART
# CONFIG_MCUMGR_TRANSPORT_UART=y

# Dependencies
# Configure dependencies for CONFIG_MCUMGR  
CONFIG_NET_BUF=y
CONFIG_ZCBOR=y
CONFIG_CRC=y

# Configure dependencies for CONFIG_MCUMGR_GRP_IMG  
CONFIG_FLASH=y
CONFIG_IMG_MANAGER=y

# Configure dependencies for CONFIG_IMG_MANAGER  
CONFIG_STREAM_FLASH=y
CONFIG_FLASH_MAP=y

# Configure dependencies for CONFIG_MCUMGR_TRANSPORT_UART 
CONFIG_BASE64=y

# STEP 1.1 - Enable SPI driver for the application
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_NOR=y
CONFIG_SPI_NOR_SFDP_DEVICETREE=y
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
# QSPI drivers are enabled by defualt for some chips.
# Disable it explicitly to be sure QSPI is disabled.
CONFIG_NORDIC_QSPI_NOR=n

    mcuboot.conf

    # Step 6.2 - MCUboot should use external flash
CONFIG_NORDIC_QSPI_NOR=n
CONFIG_BOOT_MAX_IMG_SECTORS=256

# Step 1.2 - Enable SPI driver for MCUboot
CONFIG_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_NOR=y
CONFIG_SPI_NOR_SFDP_DEVICETREE=y
CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
# QSPI drivers are enabled by defualt for some chips.
# Disable it explicitly to be sure QSPI is disabled.
CONFIG_NORDIC_QSPI_NOR=n 

# required by SPI driver
CONFIG_MULTITHREADING=y

    sysbuild.conf

    SB_CONFIG_BOOTLOADER_MCUBOOT=y
SB_CONFIG_MCUBOOT_USE_ALL_AVAILABLE_RAM=y

# Step 6.3 - Configure project to use external flash for DFU
SB_CONFIG_PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY=y
# Step 3.1 - For SPI, we need to set  this
SB_CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y

# Step 7.2 - Add b0n image
SB_CONFIG_SECURE_BOOT_NETCORE=y

# Step 7.3 - Set up multiple partitions
SB_CONFIG_MCUBOOT_UPDATEABLE_IMAGES=2

# Step 7.4 - Add support to netcore for DFU
SB_CONFIG_NETCORE_APP_UPDATE=y

# Step 7.5 - Add support to mcuboot for updating
# two cores simultaneously
SB_CONFIG_MCUBOOT_NRF53_MULTI_IMAGE_UPDATE=y

# Step 7.6 - Simultaneous FOTA does not support rollback
SB_CONFIG_MCUBOOT_MODE_OVERWRITE_ONLY=y

    Same error.

    Objective is to run Simultaneous updates for both cores of the nRF5340 for SPI with board nrf7002dk/nrf5340/cpuapp/ns

    Can you verify it works?

    Thank you.

  • 0 in reply to ioabro

    Please be verbose in sharing logs, so that I can understand what is occurring on your end.

    What is the error that you are seeing?

     

    Instead of sharing one-and-one file, please share a .zip.

     

    Kind regards,

    Håkon

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