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Clarification of GPIO configuration for SPI master

Hi all

Chapter 26.1.1 of the nRF51 series reference manual v3.0 states that the pins used by the SPI master have to be configured in the GPIO registers according to table 221.

Now, I have some points that are not quite clear to me:

  1. Are the GPIO settings only necessary for the OFF mode or for the normal operation when the SPI master is enabled? We are using the SPI master already for a while and haven't realized that the GPIO registers must be configured, but so far we didn't run into any problems...
  2. Why is it necessary that the input buffer of the SCK pin has to be connected although the pin is configured as output?

Many thanks in advance for your help!

Kind regards

  • PULL and DRIVE will still be valid for the pin configuration, so not overwritten and will always take effect.

  • Hello Ole,

    your valuable reply is more than three years old, though unfortunately I don't see any change in the nRF51 Series Reference Manual V3.0.1 regarding the configuration of GPIOs for usage as SPI pins.  The same ambiguous information can still be found in chapter 26.1.1 imposing the SCK pin to be configured with an active input buffer...

    Will there someday be a revised version of this manual ?

    This very description is even also given online for the nRF52.

    While I'm at it, I'd also like to propose changing the description for the SPI ENABLE register in table 227.  As I am writing my own SPI driver I have to rely on good information.  I had to find out the hard way that the SPI peripheral is enabled by writing a "1" to this register.  As my first assumption was to set all three bits marked as "A", I never succeeded in activating SPI on my nRF51822.  So please mark only bit 0 with an "A" in table 227.

    BTW, in the online nRF52 Product Specification I saw that bits 0-3 are marked "A", so I am confused how to start SPI there, too, if I am ever to work with this kind of chip in the future.

    2nd proposal: in the "nRF51 Series Reference Manual" please include a description of the SPI READY event register.  Only the online nRF52 Product Specification offers an adequate explanation.  The same holds for other event registers as well, like the TIMER Compare event registers in table 18.2.

    Thank you.

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