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Does the nrf51 ADC use sample and hold?

I have a high-speed signal which I would like to sample with the nrf51's ADC. The signal is periodic (80kHz) and is from a low-impedance source (op amp buffer). I don't need to sample the whole waveform - I just need to measure the amplitude of the signal at a specific point, once every few cycles. I intend to use a TIMER module and the PPI to trigger an ADC conversion to occur at a precise time.

From reading the datasheet, I understand that a 10-bit conversion will take 68us to complete. Waiting 68us to get the result is ok - I don't require a high sample rate. But does the ADC module also require the signal to be stable for 68us in order to perform the conversion? Or does the ADC hardware use a typical sample-and-hold circuit to capture the signal voltage before performing the conversion?

The datasheet seems to suggest that the signal needs to be stable for the entire conversion time. Is this the case even when voltage dividers aren't used? I would like to confirm before I rule out this solution and look for other ways.

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