nrf52 RAM Retention issue

[vishal]

Hi, In my project i would like to save 100 bytes of information in RAM before going to System-off sleep mode.I have tested the example project given in sdk11 works okay.Have used the same in my application as well.I am using softdevice S132 .Configured a button to wake up. My issue begins here :-( -After programming my board I used the push button to wake my device,the RAM data was available and works perfectly.But if I power cycle the board once,and after my device sleeps if I wake my device by pressing the push button the RAM details are not read.But what I noticed is the register GPREGRET was written to and read as expected.

-Should i take any special care while saving data to RAM?

[Hung Bui]

Hi Vishal,

Please clarify, it's not clear if you planned to retain the data when you power cycle the board, or power cycling is just part of the test process, what you want to retain is before and after you sleep after you power cycle ?

It's not possible to retain data when you power cycle.

If you test with the test code from the SDK and do a power cycle and test again, do you have the same issue ?

[vishal]

Hi Bui, I do not want to retain data after power cycle.I would like the data to be retained after it comes out of sleep.In the example code it is working but that is without Softdevice.Our application is using s132.

[Hung Bui]

Which part of the memory do you plan to retain ? Could you post your code you use for memory retention ? I'm thinking maybe the start up code may clean up the memory part you used. You may want to create a RAM section with NoInit check box checked in Project Option -> Target -> IRAM2

It's a note at section 18.2 i the nRF52 Spec v1.1 saying: Note that these registers are usually overwritten by the startup code provided with the nRF application examples.

[vishal]

Hi Bui, -I am using ARM GCC on eclipse.Below are the two function I use to read Data from RAM.And store data before going to sleep.

[vishal]

#define RESET_MEMORY_TEST_BYTE (0x0DUL) #define SIZE_OF_RAM_RETENTION_BUFFER 100 #define DEAD_BEEF 0xDEADBEEF static uint32_t ram_retention_data[SIZE_OF_RAM_RETENTION_BUFFER];

void dot_boot_up() {

	uint32_t p_ramon[1], err_code, i, verification_data;

	err_code = sd_power_gpregret_get(p_ramon);
	APP_ERROR_CHECK(error_code);

	uint32_t * volatile p_ram_test = (uint32_t *) VARIANCE_DATA_ADDRESS;
	
	//Check For power Cycle
	if ((p_ramon[0] >> 4) == RESET_MEMORY_TEST_BYTE) {

		// clear GPREGRET register before exit.
		//NRF_POWER->GPREGRET = 0;

		memset(&ram_retention_data, 0, sizeof(SIZE_OF_RAM_RETENTION_BUFFER));
		verification_data = 0;
		for (i = 0; i < SIZE_OF_RAM_RETENTION_BUFFER; i++) {
			//Read Data From RAM Location
			ram_retention_data[i] = *p_ram_test;
			*p_ram_test = 0;


			p_ram_test += 0x1;

		}


		verification_data |= ((uint8_t) ram_retention_data[INDEX_OF_VER_BYTE_0])
		<< 24;
		verification_data |= ((uint8_t) ram_retention_data[INDEX_OF_VER_BYTE_1])
		<< 16;
		verification_data |= ((uint8_t) ram_retention_data[INDEX_OF_VER_BYTE_2])
		<< 8;
		verification_data |=
		((uint8_t) ram_retention_data[INDEX_OF_VER_BYTE_3]);

		if (verification_data != DEAD_BEEF) { //check for data corruption by comparing to know seqence of data

			dprint("RAM Read Failed\r\n");

			memset(&ram_retention_data, 0,
				sizeof(SIZE_OF_RAM_RETENTION_BUFFER));
			ram_retention_data[INDEX_OF_VER_BYTE_0] = (uint8_t) ((DEAD_BEEF
				>> 24) & 0xFF);
			ram_retention_data[INDEX_OF_VER_BYTE_1] = (uint8_t) ((DEAD_BEEF
				>> 16) & 0xFF);
			ram_retention_data[INDEX_OF_VER_BYTE_2] =
			(uint8_t) ((DEAD_BEEF >> 8) & 0xFF);
			ram_retention_data[INDEX_OF_VER_BYTE_3] = (uint8_t) (DEAD_BEEF
				& 0xFF);

		} else {

			
			dprint("Success");

		}

		err_code = sd_power_gpregret_clr(0x0);
		APP_ERROR_CHECK(err_code);

	} else {
		dprint("Device Reset/Corruption\r\n");
		memset(&ram_retention_data, 0, sizeof(SIZE_OF_RAM_RETENTION_BUFFER));
		ram_retention_data[INDEX_OF_VER_BYTE_0] = (uint8_t) ((DEAD_BEEF >> 24)
			& 0xFF);
		ram_retention_data[INDEX_OF_VER_BYTE_1] = (uint8_t) ((DEAD_BEEF >> 16)
			& 0xFF);
		ram_retention_data[INDEX_OF_VER_BYTE_2] = (uint8_t) ((DEAD_BEEF >> 8)
			& 0xFF);
		ram_retention_data[INDEX_OF_VER_BYTE_3] = (uint8_t) (DEAD_BEEF & 0xFF);

	}
}


void dot_enter_sleep(void) {

	uint32_t * volatile p_ram_test = (uint32_t *) VARIANCE_DATA_ADDRESS;
	uint32_t err_code, i = 0;
	uint32_t ramon = 0;


	nrf_gpio_cfg_sense_input(16, NRF_GPIO_PIN_PULLUP, NRF_GPIO_PIN_SENSE_LOW);

	nrf_delay_ms(1);
	for (i = 0; i < SIZE_OF_RAM_RETENTION_BUFFER; i++) {

		*p_ram_test = 0;// Clear RAM Locations

		p_ram_test += 0x1;
	}

	p_ram_test = (uint32_t *) VARIANCE_DATA_ADDRESS;//Resest Address

	err_code = sd_power_gpregret_set((RESET_MEMORY_TEST_BYTE << 4));
	APP_ERROR_CHECK(err_code);
	nrf_delay_ms(1);

	ramon = POWER_RAMON_ONRAM0_RAM0On << POWER_RAMON_ONRAM0_Pos
	| POWER_RAMON_ONRAM1_RAM1On << POWER_RAMON_ONRAM1_Pos
	| POWER_RAMON_OFFRAM0_RAM0On << POWER_RAMON_OFFRAM0_Pos
	| POWER_RAMON_OFFRAM1_RAM1On << POWER_RAMON_OFFRAM1_Pos;


	err_code = sd_power_ramon_set(ramon);
	APP_ERROR_CHECK(err_code);

	p_ram_test = (uint32_t *) VARIANCE_DATA_ADDRESS;
	
	for (i = 0; i < SIZE_OF_RAM_RETENTION_BUFFER; i++) {

		
		*p_ram_test = 0xAA; //Test Dummy Value
		nrf_delay_ms(1);



	}
	
	
	
	__DSB();

	dprint("Sleep\r\n");

	nrf_delay_ms(10);
	sd_power_system_off();

	dprint("Sleep error\r\n");

}