FDS Update Effecting UART Transmit

[jsample]

I've noticed that if I have data queued to go out over the uart (using app_uart_fifo) if I do an fds_record_update the UART TX is effected. You can see what's happening in the logic analyzer screenshot below. The FDS line goes high when fds_record_update is called and low once the FDS_EVT_UPDATE event is received.

Is this just to be expected since FDS seems to have higher priority or is there something I can do to improve this?

[Jørgen Holmefjord]

You might be using the EasyDMA, but if you look at the IRQ handler implementation in app_uart_fifo library, you can see that only a single byte is setup for transfer at a time:

case NRF_DRV_UART_EVT_TX_DONE:
// Get next byte from FIFO.
if (app_fifo_get(&m_tx_fifo, tx_buffer) == NRF_SUCCESS)
{
	(void)nrf_drv_uart_tx(&app_uart_inst, tx_buffer, 1);
}

If a higher priority task is blocking the library, the IRQ handler will not be able to setup transfer of a new byte until the higher priority task is done.