SAADC has strange periodic noise after power off/on

[kxJiang]

Hi，guys. I have a problem when dealing with NRF52's SAADC using nRF5_SDK_13.0.0_04a0bfd. The problem is after downloading and run the program using JLink, everything works fine, the values sampled by SAADC have little jitters. But if we shutdown NRF52 then power it on, sampled results get large periodic jitters. Below are two plot pictures contains the raw data sampled by SAADC in two situations with 500HZ sample rate.The input signal is 5HZ sin wave, you can see from the first figure that the sampled signal is just ok, but the second has large jitters. The only difference is we issued a power on sequence in the second situation. In all situations we usenrf_drv_saadc_sample_convert to get the adc result. the configuration of saadc is single end, 1/6 gain,burst enabled and 4x oversamle.

Another thing is that, when we use nRF5_SDK_12 with ppi and DMA, there're no such jitters in whatever situation. Any suggestions to figure out such problem? Thanks!

[kxJiang]

Hi, sorry for the late reply. I have figured out the problem by comparing the two projects. The difference is that I did not enable DC-DC in SDK12.0, while enabling it in SDK13.0. That is if I add the code sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE);afterble_stack_init();,That strange thing will happen, the saadc will have large jitters when power off/on. When I remove the sd_power_dcdc_mode_set(NRF_POWER_DCDC_ENABLE); ,everything works fine. But I still don't know why. Any comments on that? Thanks for your kindness!

[kxJiang]

Hi, we use the DC-DC's 1.3V output as OP's reference voltage. But if that's the problem, why It is normal without power off/on.

[Jørgen Holmefjord]

The reason you are not seeing this issue before power cycling the chip is that after programming the chip will be in debug mode. The DC/DC operates in two modes, normal and refresh mode. In debug mode the chip will draw much current, and then the most efficient mode will be automatically selected. The running mode will not be DC/DC refresh, and maybe not even DC/DC normal mode, as LDO normal mode might be best suited since it provide the most current. The DC/DC regulator is a switching regulator, which might introduce much noise. If you want to use DC/DC mode to save current during normal run, I would recommend that you disable DC/DC mode before sampling the SAADC, and enable it again when sampling is completed. This should reduce the noise.

[kxJiang]

But when we reset the board using nRESET pin without power cycling, we will not have this issue. Does that mean in such situation, even though we try to enable DC/DC, the chip may still use LDO as it is more efficient? Why reset differs from power cycling in such circumstance. In my situation, the chip uses LDO when reset without power cycling since the sadc has little noise, but uses DC/DC when power cycling since there's much noise. In both cases, I enabled the DC/DC in my code. Any detailed information on how the chip decide which regulator to use in these two cases ,depending on current consumption? I hope u can stand my verbose question. Thanks for your help.

[Jørgen Holmefjord]

Have you enabled pinreset using the symbol CONFIG_GPIO_AS_PINRESET? You might still be in debug mode until power cycling the board. Unfortunately, we do not have any more detailed information on when the DC/DC will be active, it will choose the most suited mode depending on the current draw.