Hi,
Ours is a battery (LiPo) operated device with VDDH= 3.0 to 4.2V. One of the reasons for using nRF52840 is to avoid an expensive external DCDC IC. But due to the Anomaly 197 (DCDC of REG0 not functional) in nRF52840, It seems we have no choice but to use LDO in Reg0 stage. So I am trying to find out how badly does this affect our battery life.
Questions:
1. For a varying Vddh (4.2-3V) and a fixed Vdd (=3V or 3.3V set by regout0 register), what's the efficiency of the LDO in Reg0 stage? The LDO efficiency is usually calculated as Vout*Iout/ (Vin*(Iin+Iq)). For this we need to know the quiescent current (Iq) of the LDO. How much is it? Is this mentioned anywhere in the documentation? We will need this information to make a call on whether to use the inbuilt nRF52840 LDO or an external DCDC for Vddh to Vdd conversion.
2. What happens if we set regout0 to have Vdd=3.6V and Vddh drops below that due to battery discharge. Does Vdd follow Vddh as expected in a normal LDO?
3. Can we dynamically change the Vdd voltage to maximise LDO efficiency? i.e. When Vddh in the range of 4.2-3.7V, we set Vdd=3.6V and as Vddh drops due to battery discharge, we change the regout0 register value to set Vdd at much lower value automatically via firmware (and then do a softreset). Objective is to minimise the difference between Vddh and Vdd which in turns maximise LDO efficiency.
4. Is there any Rev 2 of nRF52840 in the pipeline when anomaly 197 (and hopefully 202) will get fixed?
