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  • Case ID: 222839
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NRF52840 SPIM3

lpham

Hi,

I am using the 2 NRF52840 boards, rev 1.  I am using SDK 15.2.  The first board is running the NRFX_SPIM example.  The second board is running the SPIS example.  The rx_delay is set to 0x02.

When I configured the SPIM to run at 4MHz.  The SPIM and SPIS sometimes get the correct message.  and sometimes get data value of all F's.

When I configured the SPIM to run at 32MHz.  The SPIM and SPIS received data is always incorrect.

Any ideas?  Has anyone tried using the NRFX_SPIM and SPIS example projects together?

Thanks,

SPIM configured to run at 4MHz result.  Below is the result from the SPIM.

0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF |.....
0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF 4E 6F 72 64 69 63 31|.Nordic1
0> <info> app: 32 33 34 35 36 37 38 39|23456789
0> <info> app: 30 31 32 33 34 35 36 37|01234567
0> <info> app: 38 39 30 31 32 33 34 35|89012345
0> <info> app: 36 37 38 39 30 |67890
0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF |.....
0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF 4E 6F 72 64 69 63 31|.Nordic1
0> <info> app: 32 33 34 35 36 37 38 39|23456789
0> <info> app: 30 31 32 33 34 35 36 37|01234567
0> <info> app: 38 39 30 31 32 33 34 35|89012345
0> <info> app: 36 37 38 39 30 |67890

Below is the result of the SPIM when configured to run at 32MHz.

0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF FF FF DF E5 C9 D3 C7|........
0> <info> app: 63 64 67 68 6A 6C 6E 38|cdghjln8
0> <info> app: 39 30 31 32 33 FF FF FF|90123...
0> <info> app: FF FF B9 B0 B1 B2 B3 B4|........
0> <info> app: B5 B6 B7 B8 B9 |.....
0> <info> app: Transfer completed.
0> <info> app: Received:
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF FF FF FF|........
0> <info> app: FF FF FF FF FF |.....

Below is the result of SPIS when configured to run at 32MHz.

Transfer completed

0> <info> app: 6F 72 64 69 63 31 32 33|ordic123
0> <info> app: 34 35 36 37 38 39 30 31|45678901
0> <info> app: 32 33 34 35 36 37 38 39|23456789
0> <info> app: 30 31 32 33 34 35 36 37|01234567
0> <info> app: 70 72 60 |pr`

Transfer completed
0> <info> app: 37 B9 32 34 B1 98 99 19|7.24....
0> <info> app: 9A 1A 9B 1B 9C 1C 98 18|........
0> <info> app: 99 19 9A 1A 9B 1B 9C 1C|........
0> <info> app: 98 18 99 19 9A 1A 9B 1B|........
0> <info> app: 9C 1C 98 |...

  • 0 in reply to hmolesworth

    I also switched to P1.15 earlier but it had the same behavior.

  • 0 in reply to hmolesworth

    I looked at all the available GPIOs that support the high drive mode, and tried them out for the MISO but they all showed the same behavior.  

    I shorted the SB20, and cut SB10 to use P0.23 but it also exhibit the same behavior as other GPIOs. 

    Since P0.27 worked good, I swapped the MISO and MOSI but the MISO still shows bad data output.  

  • 0 in reply to lpham

    This is just a guess, but have you tried enabling the internal pullups for the SPI pins? (I see NOPULL in the code snipped above, so I suspect not.)

    I have a project where I'm using the high speed SPI bus at 32MHz for an ILI9341 display. I'm able to correctly do reads and writes of its video memory. (I don't actually use the read memory feature much, but I did test it at one point just as a sanity check.)

    -Bill

  • 0 in reply to wpaul

    I am using MODE0.

    I pulldown MOSI, MISO, SCK.  I pullup CS. I applied the change to both the SPIM and SPIS projects.

    It didn't solve the problem with the MISO signal.

  • +1

    I tried with out-of-box software on 2 x pca10056 nRF52 DKs SDK 15.2.0 and get good operation at 8MHz and 16MHz provided the hardware CS is disabled; the issue seems to be too short a setup time between /CS and SCK going active. It partially works at 32MHz, but every other packet gets slightly damaged. SPIM:

    // This is working reliably at 16MHz, SPIM to SPIS both directions
// Only change is to SPIM, but SPIS works better in release mode
    nrfx_spim_config_t spi_config = NRFX_SPIM_DEFAULT_CONFIG;
    spi_config.frequency      = NRF_SPIM_FREQ_16M;   // <======== !
    spi_config.ss_pin         = NRFX_SPIM_SS_PIN;
    spi_config.miso_pin       = NRFX_SPIM_MISO_PIN;
    spi_config.mosi_pin       = NRFX_SPIM_MOSI_PIN;
    spi_config.sck_pin        = NRFX_SPIM_SCK_PIN;
    spi_config.dcx_pin        = NRFX_SPIM_DCX_PIN;
    spi_config.use_hw_ss      = false; //true;       // <======== !
    spi_config.ss_active_high = false;
    spi_config.mode           = NRF_SPIM_MODE_0;
    spi_config.rx_delay       = 0x02;
    spi_config.ss_duration    = 0x02;

    APP_ERROR_CHECK(nrfx_spim_init(&spi, &spi_config, spim_event_handler, NULL));

    // High power output pins
    nrf_gpio_cfg(NRFX_SPIM_SS_PIN,
                 NRF_GPIO_PIN_DIR_OUTPUT,
                 NRF_GPIO_PIN_INPUT_DISCONNECT,
                 NRF_GPIO_PIN_NOPULL,
                 NRF_GPIO_PIN_H0H1,       // Require High Drive high/low level
                 NRF_GPIO_PIN_NOSENSE);

    // High power output pins
    nrf_gpio_cfg(NRFX_SPIM_MOSI_PIN,
                 NRF_GPIO_PIN_DIR_OUTPUT,
                 NRF_GPIO_PIN_INPUT_DISCONNECT,
                 NRF_GPIO_PIN_NOPULL,
                 NRF_GPIO_PIN_H0H1,       // Require High Drive high/low level
                 NRF_GPIO_PIN_NOSENSE);

    // High power output pins
    nrf_gpio_cfg(NRFX_SPIM_SCK_PIN,
                 NRF_GPIO_PIN_DIR_OUTPUT,
                 NRF_GPIO_PIN_INPUT_DISCONNECT,
                 NRF_GPIO_PIN_NOPULL,
                 NRF_GPIO_PIN_H0H1,       // Require High Drive high/low level
                 NRF_GPIO_PIN_NOSENSE);

    NRF_LOG_INFO("NRFX SPIM example started.");

    Note SPIS works better if compiled in Release build or with better optimisation, SPIS:

        nrf_drv_spis_config_t spis_config = NRF_DRV_SPIS_DEFAULT_CONFIG;
    spis_config.csn_pin               = APP_SPIS_CS_PIN;
    spis_config.miso_pin              = APP_SPIS_MISO_PIN;
    spis_config.mosi_pin              = APP_SPIS_MOSI_PIN;
    spis_config.sck_pin               = APP_SPIS_SCK_PIN;
    spis_config.mode                  = NRF_SPIS_MODE_0;

    APP_ERROR_CHECK(nrf_drv_spis_init(&spis, &spis_config, spis_event_handler));

    // High power output pins
    nrf_gpio_cfg(APP_SPIS_MISO_PIN,
                 NRF_GPIO_PIN_DIR_OUTPUT,
                 NRF_GPIO_PIN_INPUT_DISCONNECT,
                 NRF_GPIO_PIN_NOPULL,
                 NRF_GPIO_PIN_H0H1,       // Require High Drive high/low level
                 NRF_GPIO_PIN_NOSENSE);

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