nrf51822's original interrupt priority

[snow]

Hi everyone, I want to know the original interrupt priority of nrf51822, without using soft device or using NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority). I also want to know whether can I find this priority information through the nrf51822's datasheet or not. Thank you.

[John]

Hi,

It does not appear that the interrupt default priority levels are discussed in the nRF51 reference manual. This is appropriate because this is really defined by ARM and not Nordic. If I read the online ARM Cortex M0 information at the ARM Information center correctly interrupts and exceptions will all start with a priority level of 0. There is an exception for the Reset, HardFault, and NMI exceptions that have a fixed negative priority (lower priority number = higher priority).

Regards, John

[Annim]

Try do run debug session from keil using segger jlink lite. You will find the priority number down in watch windowfor the routine. I debug in that way if i went to hard fault or so. Also try to look for defines like NRF_APP_PRIORITY_LOW define, where interrupt priority are defined. You will know what number is leagal to use or not while SD enabled or not. if you do not able to find this define, use ransacagent to find the text in Nordic folder pointed, will give you where such defines are mentioned! Good luck,

[snow]

Hi John,

Thank you for your kindness and your answer. I read ARM Cortex M0 datasheet, and find what you have said. But that's not my best. I find the interrupts number of nrf51822 as follows,

Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,
SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,

/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */

POWER_CLOCK_IRQn = 0, RADIO_IRQn = 1, UART0_IRQn = 2, SPI0_TWI0_IRQn = 3,
SPI1_TWI1_IRQn = 4, GPIOTE_IRQn = 6, ADC_IRQn = 7, TIMER0_IRQn = 8,
TIMER1_IRQn = 9, TIMER2_IRQ = 10, RTC0_IRQn = 11, TEMP_IRQn = 12,
RNG_IRQn = 13, ECB_IRQn = 14, CCM_AAR_IRQn = 15, WDT_IRQn = 16,
RTC1_IRQn = 17, QDEC_IRQn = 18, LPCOMP_IRQn = 19, SWI0_IRQn = 20,
SWI1_IRQn = 21, SWI2_IRQn = 22, SWI3_IRQn = 23, SWI4_IRQn = 24,
SWI5_IRQn = 25.

When these nrf51822's interrupts in their default priority, in which their priority don't be modified by using NVIC_SetPriority(), I want to know the processing sequence if many interrupts are triggered at the same time. And I want to know the processing sequence in the case of not using the Soft Device. I look forward to hearing from you soon.

[snow]

Hi Annim,

Thank you for your kindness and comments. Do you mean that I can find the interrupt number, just like the following,

Reset_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,

/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */

POWER_CLOCK_IRQn = 0, RADIO_IRQn = 1, UART0_IRQn = 2, SPI0_TWI0_IRQn = 3, SPI1_TWI1_IRQn = 4, GPIOTE_IRQn = 6, ADC_IRQn = 7, TIMER0_IRQn = 8, TIMER1_IRQn = 9, TIMER2_IRQ = 10, RTC0_IRQn = 11, TEMP_IRQn = 12, RNG_IRQn = 13, ECB_IRQn = 14, CCM_AAR_IRQn = 15, WDT_IRQn = 16, RTC1_IRQn = 17, QDEC_IRQn = 18, LPCOMP_IRQn = 19, SWI0_IRQn = 20, SWI1_IRQn = 21, SWI2_IRQn = 22, SWI3_IRQn = 23, SWI4_IRQn = 24, SWI5_IRQn = 25.

[Vidar Berg]

Interrupt handling on the nRF51 series is the same as with other cortex-M0 based controllers. The Cortex-M0 generic user guide does therefore apply to the nRF51 as well. See section 4.2.6 for details about the interrupt priorities.

There are 4 programmable interrupts available on all interrupts besides the fixed ones on Reset(-3), NMI(-2) and hardfault(-1). 0 is the highest programmable priority, and 3 is the lowest. Also note that an interrupt is set to the highest priority at startup unless explicitly set with NVIC_NVIC_SetPriority().

Just for reference: the application can use interrupt priorities APP(L) (3) and APPL(H) (1) when a softdevice is enabled. The figure below from S110-SDS chapter 11.2 illustrates what instances that uses the available priorities. Here you can see that the highest programmable priority(0) is used by the lower stack, hence not available to the application.