Slave select pin always low

[dkj047]

Hi 

The slave select (ss) pin during the spi communication is always low even when i make it high to release the spi bus. It looks to me that I'm not actually controlling the ss pin. 

I am using nrf52840, soft device is enabled.

My spi open code looks like following:

bool spi_open(uint8_t index, nrf_drv_spi_frequency_t freq, nrf_drv_spi_mode_t mode)
{

  if (index == SPI0)
  {
    nrf_drv_spi_config_t spi0_config = NRF_DRV_SPI_DEFAULT_CONFIG;

    spi0_config.miso_pin = SPI0_MISO_PIN;
    spi0_config.mosi_pin = SPI0_MOSI_PIN;
    spi0_config.sck_pin = SPI0_SCK_PIN;  
      
    spi0_config.ss_pin = SDCARD_CS1;
    spi0_config.frequency = freq;
    spi0_config.mode = mode;
    spi0_config.orc = 0x00;

    APP_ERROR_CHECK(nrf_drv_spi_init(&spi_0, &spi0_config, NULL, NULL)); // with blocking mode
  }
  else if (index == SPI1)
  {
    nrf_drv_spi_config_t spi1_config = NRF_DRV_SPI_DEFAULT_CONFIG;

    spi1_config.miso_pin = SPI1_MISO_PIN;
    spi1_config.mosi_pin = SPI1_MOSI_PIN;
    spi1_config.sck_pin = SPI1_SCK_PIN;
#if (SDCARD == ON)
    spi1_config.ss_pin =SDCARD_CS;
#endif

    spi1_config.frequency = freq;
    spi1_config.mode = mode;
    spi1_config.orc = 0x00;

    APP_ERROR_CHECK(nrf_drv_spi_init(&spi_1, &spi1_config, NULL, NULL)); // with blocking mode
  }
}

[dkj047]

Hi 

I got solution for this, the SPIM driver makes the slave select pin active high, making the pin low after the spi transfer is done and we can not make it high. I used SPI driver instead of SPIM driver to make the slave select pin high when there is no spi transfer. 

The driver uses slave select pin as active high during transfer. Changing from nrfx_spim.c to nrfx_spi.c resolved the issue.

/**
 * @brief SPIM master driver instance configuration structure.
 */
typedef struct
{
    uint8_t sck_pin;      ///< SCK pin number.
    uint8_t mosi_pin;     ///< MOSI pin number (optional).
                          /**< Set to @ref NRFX_SPIM_PIN_NOT_USED
                           *   if this signal is not needed. */
    uint8_t miso_pin;     ///< MISO pin number (optional).
                          /**< Set to @ref NRFX_SPIM_PIN_NOT_USED
                           *   if this signal is not needed. */
    uint8_t ss_pin;       ///< Slave Select pin number (optional).
                          /**< Set to @ref NRFX_SPIM_PIN_NOT_USED
                           *   if this signal is not needed. */
    bool ss_active_high;  ///< Polarity of the Slave Select pin during transmission.
    uint8_t irq_priority; ///< Interrupt priority.
    uint8_t orc;          ///< Over-run character.
                          /**< This character is used when all bytes from the TX buffer are sent,
                               but the transfer continues due to RX. */
    nrf_spim_frequency_t frequency; ///< SPI frequency.
    nrf_spim_mode_t      mode;      ///< SPI mode.
    nrf_spim_bit_order_t bit_order; ///< SPI bit order.
#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED) || defined(__NRFX_DOXYGEN__)
    uint8_t              dcx_pin;     ///< D/CX pin number (optional).
    uint8_t              rx_delay;    ///< Sample delay for input serial data on MISO.
                                      /**< The value specifies the delay, in number of 64 MHz clock cycles
                                       *   (15.625 ns), from the the sampling edge of SCK (leading edge for
                                       *   CONFIG.CPHA = 0, trailing edge for CONFIG.CPHA = 1) until
                                       *   the input serial data is sampled.*/
    bool                 use_hw_ss;   ///< Indication to use software or hardware controlled Slave Select pin.
    uint8_t              ss_duration; ///< Slave Select duration before and after transmission.
                                      /**< Minimum duration between the edge of CSN and the edge of SCK and minimum
                                       *   duration of CSN must stay inactive between transactions.
                                       *   The value is specified in number of 64 MHz clock cycles (15.625 ns).
                                       *   Supported only for hardware controlled Slave Select.*/
#endif
} nrfx_spim_config_t;

Thanks and regards

[Jared]

Hi,

Good that you found the solution and returned with it.

regards

Jared