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ARM Cortex-M4(F) Version used in nRF52?

I'm not sure how often the Cortex-M4(F) design from ARM is updated, but what is version used in Nordic nRF52810/52832 devices?  I want to know what ARM documentation version I should be looking at for the generic user guide/technical reference manual.  See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.subset.cortexm.m4/index.html

Sorry if this information is posted in Nordic datasheet/infocenter, but I didn't see it beyond a generic "reference ARM Cortex user guide".

Thanks

  • Hi, 

    what is version used in Nordic nRF52810/52832 devices?

    It is Cortex-M4 r0p1. You will see the information when the J-Link Commander starting and connecting to the device like this. 

    -Amanda H.

  • Okay, thank you Amanda.  So is there not any documentation of this value elsewhere (e.g. infocenter table, FICR reg, nRF SDK)?  Not that I am expecting it to change a lot, just wondering for future reference.

  • If you use the J-Link tool to connect the board, it can read the CPUID reg as:

    Connecting to target via SWD
    Found SW-DP with ID 0x2BA01477
    Found SW-DP with ID 0x2BA01477
    Scanning AP map to find all available APs
    AP[2]: Stopped AP scan as end of AP map has been reached
    AP[0]: AHB-AP (IDR: 0x24770011)
    AP[1]: JTAG-AP (IDR: 0x02880000)
    Iterating through AP map to find AHB-AP to use
    AP[0]: Core found
    AP[0]: AHB-AP ROM base: 0xE00FF000
    CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
    Found Cortex-M4 r0p1, Little endian.
    FPUnit: 6 code (BP) slots and 2 literal slots
    CoreSight components:
    ROMTbl[0] @ E00FF000
    ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
    ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 003BB002 DWT
    ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 002BB003 FPB
    ROMTbl[0][3]: E0000000, CID: B105E00D, PID: 003BB001 ITM
    ROMTbl[0][4]: E0040000, CID: B105900D, PID: 000BB9A1 TPIU
    ROMTbl[0][5]: E0041000, CID: B105900D, PID: 000BB925 ETM
    Cortex-M4 identified.
    J-Link>

    -Amanda H.

  • Try this:

       NRF_LOG_INFO("nRF52832 CPUID 0x%08X, PFR0 0x%08X, PFR0 0x%08X", SCB->CPUID, SCB->PFR[0], SCB->PFR[1]);
       // <info> app: nRF52832 CPUID 0x410FC241, PFR0 0x00000030, PFR0 0x00000200
       // The CPUID Base Register bit assignments are:
       //  IMPLEMENTER  bits[31:24]  Implementer code assigned by ARM. Reads as 0x41 for a processor implemented by ARM.
       //  VARIANT      bits[23:20]  Implementation Defined variant number.
       //  ARCHITECTURE bits[19:16]  Reads as 0xF, see About the CPUID scheme on page B4-644.
       //  PARTNO       bits[15:4]         Implementation Defined part number.
       //  REVISION     bits[ 3:0]       Implementation Defined revision number
       NRF_LOG_INFO("nRF52832 CPUID.IMPLEMENTER  bits[31:24] 0x%08X", (SCB->CPUID & SCB_CPUID_IMPLEMENTER_Msk)  >> SCB_CPUID_IMPLEMENTER_Pos);
       NRF_LOG_INFO("nRF52832 CPUID.VARIANT      bits[23:20] 0x%08X", (SCB->CPUID & SCB_CPUID_VARIANT_Msk)      >> SCB_CPUID_VARIANT_Pos);
       NRF_LOG_INFO("nRF52832 CPUID.ARCHITECTURE bits[19:16] 0x%08X", (SCB->CPUID & SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
       NRF_LOG_INFO("nRF52832 CPUID.PARTNO       bits[15:4]  0x%08X", (SCB->CPUID & SCB_CPUID_PARTNO_Msk)       >> SCB_CPUID_PARTNO_Pos);
       NRF_LOG_INFO("nRF52832 CPUID.REVISION     bits[ 3:0]  0x%08X", (SCB->CPUID & SCB_CPUID_REVISION_Msk)     >> SCB_CPUID_REVISION_Pos);

    Output on nRF52832 (note same code as reported by J-Link):

    <info> app: nRF52832 CPUID 0x410FC241, PFR0 0x00000030, PFR0 0x00000200
    <info> app: nRF52832 CPUID.IMPLEMENTER bits[31:24] 0x00000041

    <info> app: nRF52832 CPUID.VARIANT bits[23:20] 0x00000000
    <info> app: nRF52832 CPUID.ARCHITECTURE bits[19:16] 0x0000000F
    <info> app: nRF52832 CPUID.PARTNO bits[15:4] 0x00000C24
    <info> app: nRF52832 CPUID.REVISION bits[ 3:0] 0x00000001

    See ARM v7-M Architecture Technical Manual at armv7m_arm.pdf

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