Which GPIO is used to wake up NRF52832 from System_Off

[ChrisR1]

Hi,

I use a board from Adafruit with NRF52832 to make a POC (Proff Of Concept) (Adafruit Feather nRF52 Bluefruit LE - nRF52832 - PRODUCT ID: 3406).

I use the Arduino IDE and a library "LOW POWER" for NRF52832 (https://github.com/mristau/Arduino_nRF5x_lowPower).

I have 5 push buttons connected to the GPIO pins : 16,15, 7, 11 and 27 which supports interrupts.

Today I use the "deep sleep mode" of the NRF52832 (System_Off) and I attach interrupts to the GPIO ports 16,15,7,11,27 to wake up the module NRF52832. And all running very well.

But now I need to go further, and I need to read/know what GPIO port has been used to wake up the system, the 16, 15,7, 11 or 27?

I tried to read the state of this digital port, but it runs only if you keep the button pushed a "long time" (the necessary time to wake up and setup the NRF52832). And in the real life, for my POC, it's not possible to keep the button pushed.

I need your help to know if it's possible with NFR52832 to know what GPIO:interrupt wake up the system when the device is in POWER_MODE_OFF?

And if it's possible, can you send me samples code to help me?

Thank you very much for your hepl.

Best regards.

[ChrisR1]

Dear Jorgen,

Thank you. I already try and it don't works. Perhaps I made a mistake and I will check it. But I found this documents, dou you think it could explain why LATCH REGISTER is always to "1" even if I use this comand : "

NRF_GPIO->LATCH = NRF_GPIO->LATCH;

https://infocenter.nordicsemi.com/topic/errata_nRF52832_Rev2/ERR/nRF52832/Rev2/latest/anomaly_832_210.html

Thank you.

BR

[210] GPIO: Bits in GPIO LATCH register are incorrectly set to 1

This anomaly applies to IC Rev. Revision 2, build codes CIAA-Ex0, QFAA-Ex0, QFAB-Ex0.

It was inherited from the previous IC revision Revision 1.

Symptoms

The GPIO.LATCH[n] register is unexpectedly set to 1 (Latched).

Conditions

Set GPIO.PIN_CNF[n].SENSE at low level (3) at the same time as PIN_CNF[n].INPUT is set to Connect (0).

Consequences

The GPIO.LATCH[n] register is set to 1 (Latched). This could have side effects, depending on how the chip is configured to use this LATCH register.

Workaround

Always configure PIN_CNF[n].INPUT before PIN_CNF[n].SENSE.

Parent topic: New and inherited anomalies

[Jørgen Holmefjord]

It could be related. Which bits are set in the LATCH? Have you checked if the corresponding pin is configured to meet the conditions for the errata?