FATFS working on MXIC MX25R6435F but not on S25FS128S

[MichielSch]

Hello,

We have integrated the FATFS example as shown in the usbd_msc example project into our own firmware application. It works perfectly on the nRF52840dk and when we modify our own hardware with the MX25R6435F chip it also runs fine on our own hardware. Meaning I can mount the filesystem, list the filesystem contents, create files, read files and modify the files.

However when we try to run it on our hardware with S25FS128S (which is the flash chip we use in production) we can only (seemingly) write the filesystem and mount it. When we try to create new files they do seem to get written (the lower level qspi functions are being called) but the filesystem itself does not get updated.

We looked on the devzone and found these examples: https://devzone.nordicsemi.com/f/nordic-q-a/50534/qspi-block-device-issue-with-s25fs-flash-part  and https://devzone.nordicsemi.com/f/nordic-q-a/56928/qspi-32bit-addressing-mode but I was not able to get the FS to behave properly. I am however able to use the memory in both 24 and 32bit addressing mode and get similar behavior.

This are the flash_params we used: static const nrf_serial_flash_params_t m_sflash_params[] = {
    {    /*S25FS128S*/
        .read_id = { 0x01, 0x20, 0x18 },
        .capabilities = 0x00,
        .size = 16 * 1024 * 1024,
        .erase_size = 4 * 1024,
        .program_size = 256,
    }
};

The chip ID is being read just fine.

How can it be that i seem to be able to read and write the FS itself but I'm not able to add files, let alone modify them. We are running on sdk 15.2 with softdevice 140 btw. 

Looking forward to your reply,

Best regards,

Michiel

[MichielSch]

Hi Simon,

This investigation is still going on and I am also getting support from the Infineon side. For debugging purposes (tracing with a logic analyzer) I would like to reduce the clock speed of the QSPI to 4MHz. I have this line #define NRFX_QSPI_CONFIG_FREQUENCY 7 in the sdk_config. This should reduce the clock frequency to 4MHz right? However it does seem to remain at 8MHz for now. Are there any other settings I should adjust to clock the memory bus down?

Thanks and best regards,

Michiel

[Simonr]

Hi

Can you make sure that NRFX_QSPI_CONFIG_FREQUENCY is actually called by your application? What was this set to before? By default it's set to 15, which should set the speed to 2MHz. Also, how are you checking the clock speed of the QSPI? Are you using a logic analyzer or oscilloscope for example?

Best regards,

Simon

[MichielSch]

Hi Simon,

Thanks for the reply.

I am using the default config (NRF_DRV_QSPI_DEFAULT_CONFIG) just as the example does. When I trace this to the config actually used in the nrfx_qspi_init function I do see that he is using NRF_QSPI_FREQ_32MDIV4. This explains the 8MHz, but it does seem that the code completely ignores the sdk_config setting. Also why is the value in the NRF_DRV_QSPI_DEFAULT_CONFIG not the same as the default value in the sdk_config?

I checked with both a logic analyzer and scope. The logic analyzer is an older Saleae model and seems to have some trouble with the 8MHz. Here is a screenshot of the trace, taken by the scope, of the clock and the MISO line, in this particular trace you can see the chip idea being read.

It seems like the values used in the NRF_DRV_QSPI_DEFAULT_CONFIG lead to a file called apply_old_config and this file is all greyed out.

Best regards,

Michiel

[MichielSch]

Hi Simon,

Also as a follow up question with regards to the default config and device FS compatibility: Is the FatFS compatible with 24bit addressing as well or only with the 32bit addressing?

Where can I find these requirements for the FS? I probably looked over them in the example but I can't quite find them.

Thanks,

Michiel

[Simonr]

Hi

Indeed, the example does not use this sdk_config.h configuration. This is a result of the implementation of the NRFX drivers, that does not seem entirely completed on the QSPI end of things, I will report this internally, as I didn't realize this myself until now. Seems like a bug on our side. Thank you for notifying us!

As for your addressing, all memory access by the QSPI peripheral memories should be word-aligned to the external memory address space, so you can only write/read in full 32 bit words.

Best regards,

Simon