Concept of pending registers in interrupt handlers in nRF

[morpho]

Is clearing the NRF_UART_EVENT_RXDRDY really sufficient before exiting the IRQ handler? Since Cortex M4 is used, there's no need to clear the pending register (to avoid the interrupt from firing continually) or that's done by nordic internally? 

[Vidar Berg]

Thanks for the additional input hmolesworth.  The designers are aware of DSB instruction, but they still ended up with the recommendation to perform a dummy read. I'm not sure what the reasoning was. Although I agree it's not perfect considering it may get optimized away by the compiler. Either way, I think both the DSB instruction and dummy read should be redundant in most cases unless you are implementing a very minimal interrupt service routine.

morpho said:

Looking at Figure 1 here and trying to relate to your description: does writing 0 to the event register result in a signal with a value of 0 which is sent out to the NVIC?

Hmolesworth explained this best. The interrupt will be trigger again instantly if the peripheral event register still reads  '1' when you exit the interrupt handler.

The other signal is going to the PPI — Programmable peripheral interconnect, a module which let you connect EVENT registers from one peripheral to a TASK register in another. As an example, you can use the PPI to make a periodic TIMER event trigger the SAADC sample task with no CPU involvement.

morpho said:

Is there a circuit diagram that involves both the pending register

The (IRQ) pending register is in the NVIC, which is a part of the ARM Cortex M4 architecture. This module is covered by the documentation from ARM.