Hello,
I've used the TWI manager to implemented a burst of transfers to and from two devices on a single bus. Basically it waits for both devices to give a data-ready interrupt via GPIOTE, and then it schedules that block of transactions (36 in total). It runs reliably, but when I examine the bus, it looks like there is sometimes a large delay (several ms) between the start condition and the start of the transfer.
Here is a wide screenshot of the lines (so you can see how it generally runs smoothly) with the anomaly at the center:
Here's a zoomed in shot of the anomaly, with 2.26ms of delay shown:
This is especially problematic because after the interrupt, there is only 2.5ms before the data registers on the sensor will start to get overwritten (unfortunately there is no FIFO or SPI interface, otherwise this wouldn't be an issue).
My understanding is that using the TWI manager in scheduled/background mode is supposed to be non-blocking. It's clear that the transaction does start fairly quickly, but what else could be interfering with the operation like this? I do have a SPI bus configured as well (but it's not running currently, and it's using the SPI2 instance, and this manager is using TWI0, so there should be no interference). If it matters, I'm using SDK 17.1 and the latest S113 softdevice.
Thank you!
TWI Config below
#define I2C_MAX_PENDING_TRANSACTIONS 35 NRF_TWI_MNGR_DEF(m_nrf_twi0_mngr, I2C_MAX_PENDING_TRANSACTIONS, 0);
ret_code_t err_code;
nrf_drv_twi_config_t config = {
.scl = SCL1_PIN_NUMBER,
.sda = SDA1_PIN_NUMBER,
.frequency = NRF_DRV_TWI_FREQ_400K,
.interrupt_priority = APP_IRQ_PRIORITY_HIGH,
.clear_bus_init = true
};
err_code = nrf_twi_mngr_init(&m_nrf_twi0_mngr, &config);
APP_ERROR_CHECK(err_code);
