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&i2c1 status="ok" configures internal pull-up or similar?

Hello Devzone,

Working with nRF9160 SICA B1A system in package, and Nordic's ncs v1.6.1 (Zephyr RTOS 2.6.0) I recently observe that a device tree board setting i2c instance 1 to status "ok" increases floor current of a 9160 based custom board by 15uA.  I have the LTE modem in flight mode ( AT+CFUN=4 ).  I can alternately have serial configured on or off via CONFIG_SERIAL=[y|n], so long as when it's enabled in Kconfig I call a Zephyr power management API to suspend on board UART devices.

Suspending the UART | SPI | I2C devices achieves the greatest current savings out of a handful of compile time config steps Nordic Semi engineers have shared and explained over the past six weeks.  With UART suspended, e.g. high speed clock turned off in nRF9160 ARM processor, floor current drops from ~600uA to about 22uA.  This is a great savings in power use!

Most steps I've taken this Q2 of 2022 have centered about Kconfig settings in file `prj.conf`, rather than questions of hardware or lower level firmware constructs.  What is now clear however is that I can only reach single microamp floor currents when I disable all I2C peripherals in our custom board's primary board file, written of course in DTS.  To reach single uA current use, in this board file I must say:

&i2c1 {
compatible = "nordic,nrf-twim";
// status = "okay";
status = "disabled";
sda-pin = <6>;
scl-pin = <5>;
clock-frequency = <I2C_BITRATE_FAST>;
};

What additional Zephyr or hardware abstraction layer code does the `status="ok"` qualifier cause to be compiled for an I2C peripheral?  From electrical tests of our custom board, we narrowed the extra 15uA of current down to the SDA and SCL GPIOs coming out of our board's nRF9160.  We surmise there are internal pull up resistors enabled when i2c1 is itself enabled in DTS.  Is this a correct understanding?

Whether or not pull ups are responsible for SDA and SCL bleeding current onto a powered down rail, is there a Zephyr or an nrf API which can adjust pull up configs on SCL, SDA pin pairs at run time?  We need our I2C peripheral configured for active use during the fraction of time our firmware is fully active.  We need to adjust these pins' configuration as we enter deep sleep mode.  And then again as firmware wakes from deep sleep mode.

Is there a Zephyr or "HAL correct" way to make these pin changes on demand?  Or are we looking at need to write code that pries under the hood and must carefully work with the vetted, more formal and correct framework of Zephyr and Nordic libraries?

Thanks ahead of time to any who can help!

- Ted

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