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Segger Debug Out on DK can't see my target

Bret Foreman

I just got a new target board back from fab/assembly and I'm trying to use the debug out connector on the PCA10028 to program the new target.

My target is the NRF51822-CFAC-R

I've wired J19 on the DK as follows:

Pin 1 - tied to the same 3V supply that powers the DK and my target
Pin 2 - SWDIO (pin H2) on my target
Pin 3 - GND on my target
Pin 4 - SWDCLK (pin C8) on my target

In nRFgo Studio, I'm able to see the Segger on the DK but the Segger is not able to see my target device. Is there any additional setup I need to do on the DK in order to download to my device?

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    I added a 100K pull-down to the SWDCLK pin as per this thread. But that did not fix the problem. I still think it's a good idea to have this pull-down in place, though, since my target does not have it and the DK I'm using to program doesn't either. And I'm not sure if I have the latest version of the silicon where there is an internal pull-down.

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    It looks as though the 16MHz crystal is not starting. I'm not sure if that will prevent the JTAG from working but this thread seems to indicate so. I used 12pF caps on the crystal, copied from the reference design. But I see the values are rather critical as specified in section 3.6.1 of the Product Specification. I'll do some measurements and calculations and see if changing the caps will get the crystal to start. Does anyone know if that would prevent the JTAG from working?

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    Hmm. Figuring out the correct value for the load caps turns out to be harder than it should be. I looked at the white paper entitled "Crystal Oscillator Design Considerations" and the calculations it suggest are simple enough. However, it contains the following sentence:

    When buying crystals you can usually choose from a range of capacitive loads (ex: 8-20pF). When ordering a crystal you must choose a CL (ex: 12 pF) that is within the range of the CL specified for the nRF device. The CL range that nRF devices can operate in is only limited by the maximum CL (ex: CL < 16 pF). This maximum CL depends on the on-chip crystal oscillator design and is specified in the device data sheet.

    I can't find a data sheet listed here.

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    I've been looking for CL in the product specification document but I can't find it. What CL is the crystal oscillator white paper talking about?

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    To address some of this items listed above.

    1. A target board running at 3.0vdc will program fine. (The Beacon Reference design for example runs on a button cell)
    2. The Unit will flash without the High speed crystal operating.
    3. The CL value can calculated : (CL*2)-4 (for the nRF51) The 4 is the stray capacitance in pf on the pins from the ESD protection and wire bonding. Pick the nearest standard value cap. CL=8pf then load cap SB 12pf (each side!)
    4. The high speed crystal clock comes on when needed.
    5. Rev 2 and Rev 3 silicon have pull ups and pull downs on the SWD lines. No external ones are needed but will not hamper it from working either.
    6. Pin 1 on P19 is not a voltage source, it is a reference input to the Segger part telling it that there is something connected and correct Vcc..
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