LPUART nRF5340 fatal error

[Chris Burns]

I'm working on a custom board that has an nRF9160 connected to an nRF5340 and am using NCS v2.3.0. I am able to build and run applications for both chips successfully, but LPUART is generating a fatal error on the nRF5340:

[00:00:04.924,163] <err> os: >>> ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0
[00:00:04.932,403] <err> os: Current thread: 0x20008ed8 (unknown)
ASSERTION FAIL [!arch_is_in_isr()] @ WEST_TOPDIR/zephyr/kernel/sched.c:1463

This error occurs when the nRF9160 attempts to send anything. If there is no application on the nRF9160 the fatal error happens immediately after nrfx_gpiote_input_configure is called within the rdy_pin_idle function in uart_nrf_sw_lpuart.c. It seems to me that the GPIOTE interrupt for the nRF5340 RDY pin is not handled by the driver.

I have tested this exact project configuration and code on another board which has an nRF52840 instead of an nRF5340 and it can both send and receive data from the nRF9160 without issue.

In case it helps, here is the autoconf.h file generated by the Zephyr build system:

#define CONFIG_GPIO 1
#define CONFIG_GPIO_INIT_PRIORITY 40
#define CONFIG_BOARD "xxxx_a0_nrf5340_cpuapp"
#define CONFIG_BUILD_WITH_TFM 1
#define CONFIG_TFM_FLASH_MERGED_BINARY 1
#define CONFIG_FLASH_LOAD_SIZE 0x30000
#define CONFIG_SRAM_SIZE 192
#define CONFIG_FLASH_LOAD_OFFSET 0x50000
#define CONFIG_MBOX_NRFX_IPC 1
#define CONFIG_HEAP_MEM_POOL_SIZE 0
#define CONFIG_SOC "nRF5340_CPUAPP_QKAA"
#define CONFIG_SOC_SERIES "nrf53"
#define CONFIG_NUM_IRQS 69
#define CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC 32768
#define CONFIG_CLOCK_CONTROL_INIT_PRIORITY 30
#define CONFIG_FLASH_SIZE 1024
#define CONFIG_FLASH_BASE_ADDRESS 0x0
#define CONFIG_ICACHE_LINE_SIZE 32
#define CONFIG_DCACHE_LINE_SIZE 32
#define CONFIG_ROM_START_OFFSET 0x0
#define CONFIG_PINCTRL 1
#define CONFIG_CLOCK_CONTROL 1
#define CONFIG_SOC_HAS_TIMING_FUNCTIONS 1
#define CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT 1
#define CONFIG_PM 1
#define CONFIG_PM_DEVICE 1
#define CONFIG_LOG_DOMAIN_NAME ""
#define CONFIG_NRF_RTC_TIMER 1
#define CONFIG_SYS_CLOCK_TICKS_PER_SEC 32768
#define CONFIG_BUILD_OUTPUT_HEX 1
#define CONFIG_SERIAL_INIT_PRIORITY 55
#define CONFIG_TINYCRYPT 1
#define CONFIG_SERIAL 1
#define CONFIG_MAIN_STACK_SIZE 1024
#define CONFIG_MP_MAX_NUM_CPUS 1
#define CONFIG_PLATFORM_SPECIFIC_INIT 1
#define CONFIG_HAS_DTS 1
#define CONFIG_DT_HAS_ARM_ARMV8M_MPU_ENABLED 1
#define CONFIG_DT_HAS_ARM_CORTEX_M33F_ENABLED 1
#define CONFIG_DT_HAS_ARM_V8M_NVIC_ENABLED 1
#define CONFIG_DT_HAS_BOSCH_BMP388_I2C_ENABLED 1
#define CONFIG_DT_HAS_FIXED_PARTITIONS_ENABLED 1
#define CONFIG_DT_HAS_GLOBALSTAR_STX3_ENABLED 1
#define CONFIG_DT_HAS_GPIO_KEYS_ENABLED 1
#define CONFIG_DT_HAS_GPIO_LEDS_ENABLED 1
#define CONFIG_DT_HAS_MAXIM_17055_ENABLED 1
#define CONFIG_DT_HAS_MMIO_SRAM_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_MBOX_NRF_IPC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_CLOCK_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_CTRLAPPERI_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_DCNF_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_DPPIC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_EGU_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_GPIO_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_GPIOTE_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_IPC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_KMU_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_MUTEX_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_OSCILLATORS_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_PINCTRL_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_POWER_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_PWM_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_QSPI_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_REGULATORS_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_RESET_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_RTC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_SAADC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_SPIM_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_SW_LPUART_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_TIMER_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_TWIM_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_UARTE_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_USBD_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_USBREG_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_VMC_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF_WDT_ENABLED 1
#define CONFIG_DT_HAS_NORDIC_NRF53_FLASH_CONTROLLER_ENABLED 1
#define CONFIG_DT_HAS_SOC_NV_FLASH_ENABLED 1
#define CONFIG_DT_HAS_ST_LIS2DE12_I2C_ENABLED 1
#define CONFIG_DT_HAS_U_BLOX_ZOE_M8_SPI_ENABLED 1
#define CONFIG_DT_HAS_ZEPHYR_BT_HCI_ENTROPY_ENABLED 1
#define CONFIG_DT_HAS_ZEPHYR_IPC_OPENAMP_STATIC_VRINGS_ENABLED 1
#define CONFIG_DT_HAS_ZEPHYR_PSA_CRYPTO_RNG_ENABLED 1
#define CONFIG_NEWLIB_LIBC_NANO 1
#define CONFIG_NUM_METAIRQ_PRIORITIES 0
#define CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE 1024
#define CONFIG_LOG_BUFFER_SIZE 1024
#define CONFIG_MBEDTLS_CIPHER_MODE_CFB 1
#define CONFIG_MBEDTLS_CIPHER_MODE_OFB 1
#define CONFIG_MBEDTLS_RSA_C 1
#define CONFIG_MBEDTLS_SHA512_C 1
#define CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 1
#define CONFIG_MBEDTLS_LIBRARY_NRF_SECURITY 1
#define CONFIG_WARN_EXPERIMENTAL 1
#define CONFIG_PRIVILEGED_STACK_SIZE 1024
#define CONFIG_BT_BUF_CMD_TX_COUNT 10
#define CONFIG_ENTROPY_GENERATOR 1
#define CONFIG_INIT_ARCH_HW_AT_BOOT 1
#define CONFIG_NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE 4096
#define CONFIG_LOG_DEFAULT_LEVEL 3
#define CONFIG_PM_PARTITION_SIZE_PROVISION 0x280
#define CONFIG_PM_PARTITION_SIZE_B0_IMAGE 0x8000
#define CONFIG_SB_VALIDATION_INFO_MAGIC 0x86518483
#define CONFIG_SB_VALIDATION_POINTER_MAGIC 0x6919b47e
#define CONFIG_SB_VALIDATION_INFO_CRYPTO_ID 1
#define CONFIG_SB_VALIDATION_INFO_VERSION 2
#define CONFIG_SB_VALIDATION_METADATA_OFFSET 0
#define CONFIG_SB_VALIDATE_FW_SIGNATURE 1
#define CONFIG_ESB_LOG_LEVEL_INF 1
#define CONFIG_ESB_LOG_LEVEL 3
#define CONFIG_NRF_CLOUD_CLIENT_ID_SRC_COMPILE_TIME 1
#define CONFIG_NRF_CLOUD_CLIENT_ID "my-client-id"
#define CONFIG_NRF_CLOUD_ALERTS_LOG_LEVEL_INF 1
#define CONFIG_NRF_CLOUD_ALERTS_LOG_LEVEL 3
#define CONFIG_NRF_CLOUD_LOG_LEVEL_INF 1
#define CONFIG_NRF_CLOUD_LOG_LEVEL 3
#define CONFIG_TFM_UART0_TXD_PIN 4294967295
#define CONFIG_TFM_UART0_RXD_PIN 4294967295
#define CONFIG_TFM_UART0_RTS_PIN 4294967295
#define CONFIG_TFM_UART0_CTS_PIN 4294967295
#define CONFIG_NRF_GPIO0_PIN_MASK_SECURE 0x00000000
#define CONFIG_NRF_GPIO1_PIN_MASK_SECURE 0x00000000
#define CONFIG_NRF_DPPI_CHANNEL_MASK_SECURE 0x00000000
#define CONFIG_MPSL_FEM_LOG_LEVEL_INF 1
#define CONFIG_MPSL_FEM_LOG_LEVEL 3
#define CONFIG_MPSL_THREAD_COOP_PRIO 8
#define CONFIG_MPSL_WORK_STACK_SIZE 1024
#define CONFIG_MPSL_TIMESLOT_SESSION_COUNT 0
#define CONFIG_MPSL_LOG_LEVEL_INF 1
#define CONFIG_MPSL_LOG_LEVEL 3
#define CONFIG_PARTITION_MANAGER_ENABLED 1
#define CONFIG_FLASH_MAP_CUSTOM 1
#define CONFIG_SRAM_BASE_ADDRESS 0x20040000
#define CONFIG_PM_SINGLE_IMAGE 1
#define CONFIG_PM_EXTERNAL_FLASH_BASE 0x0
#define CONFIG_PM_SRAM_BASE 0x20000000
#define CONFIG_PM_SRAM_SIZE 0x80000
#define CONFIG_MGMT_FMFU_LOG_LEVEL_INF 1
#define CONFIG_MGMT_FMFU_LOG_LEVEL 3
#define CONFIG_TFM_BOARD "C:/Users/me/Repos/ncs/v2.3.0/nrf/modules/tfm/tfm/boards/nrf5340_cpuapp"
#define CONFIG_NRF_SPU_FLASH_REGION_SIZE 0x4000
#define CONFIG_FPROTECT_BLOCK_SIZE 0x4000
#define CONFIG_HW_UNIQUE_KEY_PARTITION_SIZE 0x0
#define CONFIG_NRF_SW_LPUART 1
#define CONFIG_NRFX_GPIOTE_NUM_OF_EVT_HANDLERS 2
#define CONFIG_NRF_SW_LPUART_INIT_PRIORITY 45
#define CONFIG_NRF_SW_LPUART_HFXO_ON_RX 1
#define CONFIG_NRF_SW_LPUART_MAX_PACKET_SIZE 4096
#define CONFIG_NRF_SW_LPUART_DEFAULT_TX_TIMEOUT 1000000
#define CONFIG_NRF_SW_LPUART_LOG_LEVEL_INF 1
#define CONFIG_NRF_SW_LPUART_LOG_LEVEL 3
#define CONFIG_ZTEST_MULTICORE_DEFAULT_SETTINGS 1
#define CONFIG_ZEPHYR_NRF_MODULE 1
#define CONFIG_POSIX_MAX_FDS 4
#define CONFIG_ZEPHYR_HOSTAP_MODULE 1
#define CONFIG_BOOT_SIGNATURE_KEY_FILE ""
#define CONFIG_DT_FLASH_WRITE_BLOCK_SIZE 4
#define CONFIG_MCUBOOT_USB_SUPPORT 1
#define CONFIG_ZEPHYR_MCUBOOT_MODULE 1
#define CONFIG_ZEPHYR_MBEDTLS_MODULE 1
#define CONFIG_MBEDTLS_CFG_FILE "nrf-config.h"
#define CONFIG_MBEDTLS_USER_CONFIG_FILE "nrf-config-user.h"
#define CONFIG_MBEDTLS_PKCS5_C 1
#define CONFIG_MBEDTLS_PSA_CRYPTO_C 1
#define CONFIG_PSA_WANT_ALG_HMAC_DRBG 1
#define CONFIG_PSA_HAS_KEY_DERIVATION 1
#define CONFIG_PSA_WANT_ALG_TLS12_PSK_TO_MS 1
#define CONFIG_TFM_ISOLATION_LEVEL 1
#define CONFIG_TFM_PROFILE_TYPE_MINIMAL 1
#define CONFIG_TFM_CRYPTO_ENGINE_BUF_SIZE 1
#define CONFIG_TFM_CRYPTO_CONC_OPER_NUM 1
#define CONFIG_TFM_CRYPTO_IOVEC_BUFFER_SIZE 1024
#define CONFIG_TFM_CRYPTO_PARTITION_STACK_SIZE 0x800
#define CONFIG_TFM_HALT_ON_CORE_PANIC 1
#define CONFIG_TFM_ALLOW_NON_SECURE_RESET 1
#define CONFIG_ZEPHYR_TRUSTED_FIRMWARE_M_MODULE 1
#define CONFIG_TFM_KEY_FILE_S "C:/Users/me/Repos/ncs/v2.3.0/modules/tee/tf-m/trusted-firmware-m/bl2/ext/mcuboot/root-RSA-3072.pem"
#define CONFIG_TFM_KEY_FILE_NS "C:/Users/me/Repos/ncs/v2.3.0/modules/tee/tf-m/trusted-firmware-m/bl2/ext/mcuboot/root-RSA-3072_1.pem"
#define CONFIG_TFM_CMAKE_BUILD_TYPE_MINSIZEREL 1
#define CONFIG_TFM_PARTITION_PLATFORM_CUSTOM_REBOOT 1
#define CONFIG_TFM_IMAGE_VERSION_S "0.0.0+0"
#define CONFIG_TFM_IMAGE_VERSION_NS "0.0.0+0"
#define CONFIG_TFM_MCUBOOT_IMAGE_NUMBER 1
#define CONFIG_TFM_IPC 1
#define CONFIG_TFM_PSA_TEST_NONE 1
#define CONFIG_TFM_LOG_LEVEL_SILENCE 1
#define CONFIG_TFM_PARTITION_CRYPTO 1
#define CONFIG_TFM_PARTITION_PLATFORM 1
#define CONFIG_TFM_CRYPTO_RNG_MODULE_ENABLED 1
#define CONFIG_MBEDTLS_LEGACY_CRYPTO_C 1
#define CONFIG_PM_PARTITION_SIZE_TFM_SRAM 0x8000
#define CONFIG_PM_PARTITION_SIZE_BL2 0x0
#define CONFIG_PM_PARTITION_SIZE_TFM 0x8000
#define CONFIG_PM_PARTITION_SIZE_TFM_PROTECTED_STORAGE 0x0
#define CONFIG_PM_PARTITION_SIZE_TFM_INTERNAL_TRUSTED_STORAGE 0x0
#define CONFIG_PM_PARTITION_SIZE_TFM_OTP_NV_COUNTERS 0x0
#define CONFIG_ZEPHYR_CJSON_MODULE 1
#define CONFIG_ZEPHYR_AZURE_SDK_FOR_C_MODULE 1
#define CONFIG_ZEPHYR_MEMFAULT_FIRMWARE_SDK_MODULE 1
#define CONFIG_ZEPHYR_CIRRUS_LOGIC_MODULE 1
#define CONFIG_ZEPHYR_OPENTHREAD_MODULE 1
#define CONFIG_ZEPHYR_CANOPENNODE_MODULE 1
#define CONFIG_ZEPHYR_CHRE_MODULE 1
#define CONFIG_ZEPHYR_FATFS_MODULE 1
#define CONFIG_ZEPHYR_HAL_NORDIC_MODULE 1
#define CONFIG_HAS_NORDIC_DRIVERS 1
#define CONFIG_HAS_NRFX 1
#define CONFIG_NRFX_CLOCK 1
#define CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED 1
#define CONFIG_NRFX_DPPI 1
#define CONFIG_NRFX_GPIOTE 1
#define CONFIG_NRFX_IPC 1
#define CONFIG_NRFX_NVMC 1
#define CONFIG_NRFX_TIMER 1
#define CONFIG_NRFX_TIMER2 1
#define CONFIG_ZEPHYR_LIBLC3_MODULE 1
#define CONFIG_ZEPHYR_LITTLEFS_MODULE 1
#define CONFIG_ZEPHYR_LORAMAC_NODE_MODULE 1
#define CONFIG_ZEPHYR_LVGL_MODULE 1
#define CONFIG_ZEPHYR_LZ4_MODULE 1
#define CONFIG_ZEPHYR_NANOPB_MODULE 1
#define CONFIG_ZEPHYR_PICOLIBC_MODULE 1
#define CONFIG_ZEPHYR_TRACERECORDER_MODULE 1
#define CONFIG_ZEPHYR_UOSCORE_UEDHOC_MODULE 1
#define CONFIG_ZEPHYR_ZCBOR_MODULE 1
#define CONFIG_ZEPHYR_ZSCILIB_MODULE 1
#define CONFIG_IPC_BUS_BUFFER_SIZE 4096
#define CONFIG_IPC_THREAD_PRIORITY 3
#define CONFIG_MAX_IPC_PACKET_SIZE 1024
#define CONFIG_CK_IPC_UART1 1
#define CONFIG_CK_IPC 1
#define CONFIG_UART_1_NRF_HW_ASYNC_TIMER 2
#define CONFIG_UART_1_NRF_TX_BUFFER_SIZE 4096
#define CONFIG_UART_2_NRF_TX_BUFFER_SIZE 32
#define CONFIG_ZEPHYR_CK_IPC_MODULE 1
#define CONFIG_FW_UTILS_LIB 1
#define CONFIG_ZEPHYR_FW_UTILS_MODULE 1
#define CONFIG_NRF_MODEM_SHMEM_CTRL_SIZE 0x4e8
#define CONFIG_CRYPTOCELL_CC312_USABLE 1
#define CONFIG_CRYPTOCELL_USABLE 1
#define CONFIG_NRF_OBERON 1
#define CONFIG_NORDIC_SECURITY_BACKEND 1
#define CONFIG_NRF_SECURITY 1
#define CONFIG_GENERATE_MBEDTLS_CFG_FILE 1
#define CONFIG_MBEDTLS_PSA_CRYPTO_DRIVERS 1
#define CONFIG_PSA_DEFAULT_OFF 1
#define CONFIG_PSA_CRYPTO_ACCELERATOR_DRIVER_PRESENT 1
#define CONFIG_MBEDTLS_PSA_CRYPTO_CLIENT 1
#define CONFIG_PSA_CRYPTO_DRIVER_OBERON 1
#define CONFIG_MBEDTLS_USE_PSA_CRYPTO 1
#define CONFIG_MBEDTLS_PLATFORM_MEMORY 1
#define CONFIG_MBEDTLS_PLATFORM_C 1
#define CONFIG_MBEDTLS_MEMORY_C 1
#define CONFIG_MBEDTLS_MEMORY_BUFFER_ALLOC_C 1
#define CONFIG_MBEDTLS_ENTROPY_HARDWARE_ALT 1
#define CONFIG_MBEDTLS_AES_SETKEY_ENC_ALT 1
#define CONFIG_MBEDTLS_AES_SETKEY_DEC_ALT 1
#define CONFIG_MBEDTLS_AES_ENCRYPT_ALT 1
#define CONFIG_MBEDTLS_AES_DECRYPT_ALT 1
#define CONFIG_MBEDTLS_CHACHA20_ALT 1
#define CONFIG_MBEDTLS_POLY1305_ALT 1
#define CONFIG_MBEDTLS_ECDH_GEN_PUBLIC_ALT 1
#define CONFIG_MBEDTLS_ECDH_COMPUTE_SHARED_ALT 1
#define CONFIG_MBEDTLS_ECDSA_GENKEY_ALT 1
#define CONFIG_MBEDTLS_ECDSA_SIGN_ALT 1
#define CONFIG_MBEDTLS_ECDSA_VERIFY_ALT 1
#define CONFIG_MBEDTLS_ECJPAKE_ALT 1
#define CONFIG_MBEDTLS_SHA1_ALT 1
#define CONFIG_MBEDTLS_SHA224_ALT 1
#define CONFIG_MBEDTLS_SHA256_ALT 1
#define CONFIG_MBEDTLS_ENTROPY_FORCE_SHA256 1
#define CONFIG_MBEDTLS_ENTROPY_MAX_SOURCES 1
#define CONFIG_MBEDTLS_NO_PLATFORM_ENTROPY 1
#define CONFIG_OBERON_ONLY_PSA_ENABLED 1
#define CONFIG_OBERON_ONLY_ENABLED 1
#define CONFIG_MBEDTLS_MPI_WINDOW_SIZE 6
#define CONFIG_MBEDTLS_MPI_MAX_SIZE 384
#define CONFIG_OBERON_BACKEND 1
#define CONFIG_MBEDTLS_HMAC_DRBG_C 1
#define CONFIG_MBEDTLS_AES_C 1
#define CONFIG_MBEDTLS_HKDF_C 1
#define CONFIG_MBEDTLS_GENPRIME 1
#define CONFIG_MBEDTLS_PKCS1_V15 1
#define CONFIG_MBEDTLS_PKCS1_V21 1
#define CONFIG_MBEDTLS_SHA224_C 1
#define CONFIG_MBEDTLS_SHA256_C 1
#define CONFIG_MBEDTLS_SHA384_C 1
#define CONFIG_MBEDTLS_CIPHER_C 1
#define CONFIG_MBEDTLS_MD_C 1
#define CONFIG_NRF_802154_SOURCE_NRFXLIB 1
#define CONFIG_LC3_ENC_CHAN_MAX 1
#define CONFIG_LC3_DEC_CHAN_MAX 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_8KHZ_SUPPORT 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_16KHZ_SUPPORT 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_24KHZ_SUPPORT 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_32KHZ_SUPPORT 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_441KHZ_SUPPORT 1
#define CONFIG_LC3_ENC_SAMPLE_RATE_48KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_8KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_16KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_24KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_32KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_441KHZ_SUPPORT 1
#define CONFIG_LC3_DEC_SAMPLE_RATE_48KHZ_SUPPORT 1
#define CONFIG_ZEPHYR_NRFXLIB_MODULE 1
#define CONFIG_ZEPHYR_CONNECTEDHOMEIP_MODULE 1
#define CONFIG_HAS_CMSIS_CORE 1
#define CONFIG_HAS_CMSIS_CORE_M 1
#define CONFIG_TINYCRYPT_AES 1
#define CONFIG_TINYCRYPT_AES_CBC 1
#define CONFIG_TINYCRYPT_AES_CTR 1
#define CONFIG_TINYCRYPT_AES_CCM 1
#define CONFIG_TINYCRYPT_AES_CMAC 1
#define CONFIG_BOARD_REVISION "$BOARD_REVISION"
#define CONFIG_BOARD_XXXX_A0_NRF5340_CPUAPP_NS 1
#define CONFIG_BOARD_ENABLE_DCDC_APP 1
#define CONFIG_BOARD_ENABLE_DCDC_NET 1
#define CONFIG_BOARD_ENABLE_DCDC_HV 1
#define CONFIG_SOC_SERIES_NRF53X 1
#define CONFIG_CPU_HAS_ARM_MPU 1
#define CONFIG_CPU_HAS_NRF_IDAU 1
#define CONFIG_NRF_SPU_RAM_REGION_SIZE 0x2000
#define CONFIG_HAS_SWO 1
#define CONFIG_SOC_FAMILY "nordic_nrf"
#define CONFIG_SOC_FAMILY_NRF 1
#define CONFIG_HAS_HW_NRF_CC312 1
#define CONFIG_HAS_HW_NRF_CLOCK 1
#define CONFIG_HAS_HW_NRF_CTRLAP 1
#define CONFIG_HAS_HW_NRF_DCNF 1
#define CONFIG_HAS_HW_NRF_DPPIC 1
#define CONFIG_HAS_HW_NRF_EGU0 1
#define CONFIG_HAS_HW_NRF_EGU1 1
#define CONFIG_HAS_HW_NRF_EGU2 1
#define CONFIG_HAS_HW_NRF_EGU3 1
#define CONFIG_HAS_HW_NRF_EGU4 1
#define CONFIG_HAS_HW_NRF_EGU5 1
#define CONFIG_HAS_HW_NRF_GPIO0 1
#define CONFIG_HAS_HW_NRF_GPIO1 1
#define CONFIG_HAS_HW_NRF_GPIOTE 1
#define CONFIG_HAS_HW_NRF_IPC 1
#define CONFIG_HAS_HW_NRF_KMU 1
#define CONFIG_HAS_HW_NRF_MUTEX 1
#define CONFIG_HAS_HW_NRF_NVMC_PE 1
#define CONFIG_HAS_HW_NRF_OSCILLATORS 1
#define CONFIG_HAS_HW_NRF_POWER 1
#define CONFIG_HAS_HW_NRF_PWM0 1
#define CONFIG_HAS_HW_NRF_QSPI 1
#define CONFIG_HAS_HW_NRF_REGULATORS 1
#define CONFIG_HAS_HW_NRF_RESET 1
#define CONFIG_HAS_HW_NRF_RTC0 1
#define CONFIG_HAS_HW_NRF_RTC1 1
#define CONFIG_HAS_HW_NRF_SAADC 1
#define CONFIG_HAS_HW_NRF_SPIM4 1
#define CONFIG_HAS_HW_NRF_TIMER0 1
#define CONFIG_HAS_HW_NRF_TIMER1 1
#define CONFIG_HAS_HW_NRF_TIMER2 1
#define CONFIG_HAS_HW_NRF_TWIM3 1
#define CONFIG_HAS_HW_NRF_UARTE0 1
#define CONFIG_HAS_HW_NRF_UARTE1 1
#define CONFIG_HAS_HW_NRF_UARTE2 1
#define CONFIG_HAS_HW_NRF_USBD 1
#define CONFIG_HAS_HW_NRF_USBREG 1
#define CONFIG_HAS_HW_NRF_VMC 1
#define CONFIG_HAS_HW_NRF_WDT0 1
#define CONFIG_NRF_HW_RTC1_RESERVED 1
#define CONFIG_SOC_NRF5340_CPUAPP 1
#define CONFIG_SOC_NRF5340_CPUAPP_QKAA 1
#define CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED 1
#define CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND 1
#define CONFIG_SOC_DCDC_NRF53X_APP 1
#define CONFIG_SOC_DCDC_NRF53X_NET 1
#define CONFIG_SOC_DCDC_NRF53X_HV 1
#define CONFIG_SOC_ENABLE_LFXO 1
#define CONFIG_SOC_LFXO_CAP_INT_7PF 1
#define CONFIG_SOC_HFXO_CAP_DEFAULT 1
#define CONFIG_NRF_ENABLE_CACHE 1
#define CONFIG_NRF53_SYNC_RTC 1
#define CONFIG_SYNC_RTC_LOG_LEVEL_INF 1
#define CONFIG_SYNC_RTC_LOG_LEVEL 3
#define CONFIG_NRF53_SYNC_RTC_INIT_PRIORITY 90
#define CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT 1
#define CONFIG_NRF53_SYNC_RTC_LOG_TIMESTAMP 1
#define CONFIG_NRF53_SYNC_RTC_IPM_OUT 7
#define CONFIG_NRF53_SYNC_RTC_IPM_IN 8
#define CONFIG_IPM_MSG_CH_8_ENABLE 1
#define CONFIG_IPM_MSG_CH_8_RX 1
#define CONFIG_NRF_SOC_SECURE_SUPPORTED 1
#define CONFIG_SOC_LOG_LEVEL_INF 1
#define CONFIG_SOC_LOG_LEVEL 3
#define CONFIG_SOC_COMPATIBLE_NRF 1
#define CONFIG_ARCH "arm"
#define CONFIG_CPU_CORTEX 1
#define CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK 1
#define CONFIG_CPU_CORTEX_M 1
#define CONFIG_ISA_THUMB2 1
#define CONFIG_ASSEMBLER_ISA_THUMB2 1
#define CONFIG_COMPILER_ISA_THUMB2 1
#define CONFIG_STACK_ALIGN_DOUBLE_WORD 1
#define CONFIG_FAULT_DUMP 2
#define CONFIG_BUILTIN_STACK_GUARD 1
#define CONFIG_ARM_STACK_PROTECTION 1
#define CONFIG_ARM_NONSECURE_FIRMWARE 1
#define CONFIG_ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS 1
#define CONFIG_ARM_STORE_EXC_RETURN 1
#define CONFIG_FP16 1
#define CONFIG_FP16_IEEE 1
#define CONFIG_CPU_CORTEX_M33 1
#define CONFIG_CPU_CORTEX_M_HAS_SYSTICK 1
#define CONFIG_CPU_CORTEX_M_HAS_DWT 1
#define CONFIG_CPU_CORTEX_M_HAS_BASEPRI 1
#define CONFIG_CPU_CORTEX_M_HAS_VTOR 1
#define CONFIG_CPU_CORTEX_M_HAS_SPLIM 1
#define CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 1
#define CONFIG_CPU_CORTEX_M_HAS_CMSE 1
#define CONFIG_ARMV7_M_ARMV8_M_MAINLINE 1
#define CONFIG_ARMV8_M_MAINLINE 1
#define CONFIG_ARMV8_M_SE 1
#define CONFIG_ARMV7_M_ARMV8_M_FP 1
#define CONFIG_ARMV8_M_DSP 1
#define CONFIG_GEN_ISR_TABLES 1
#define CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE 1
#define CONFIG_ARM_TRUSTZONE_M 1
#define CONFIG_GEN_IRQ_VECTOR_TABLE 1
#define CONFIG_ARM_MPU 1
#define CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE 32
#define CONFIG_MPU_ALLOW_FLASH_WRITE 1
#define CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE 32
#define CONFIG_ARM 1
#define CONFIG_ARCH_IS_SET 1
#define CONFIG_ARCH_LOG_LEVEL_INF 1
#define CONFIG_ARCH_LOG_LEVEL 3
#define CONFIG_LITTLE_ENDIAN 1
#define CONFIG_TRUSTED_EXECUTION_NONSECURE 1
#define CONFIG_HW_STACK_PROTECTION 1
#define CONFIG_KOBJECT_TEXT_AREA 256
#define CONFIG_KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 100
#define CONFIG_KOBJECT_RODATA_AREA_EXTRA_BYTES 16
#define CONFIG_GEN_PRIV_STACKS 1
#define CONFIG_ARCH_IRQ_VECTOR_TABLE_ALIGN 4
#define CONFIG_IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 1
#define CONFIG_GEN_SW_ISR_TABLE 1
#define CONFIG_ARCH_SW_ISR_TABLE_ALIGN 4
#define CONFIG_GEN_IRQ_START_VECTOR 0
#define CONFIG_ARCH_HAS_SINGLE_THREAD_SUPPORT 1
#define CONFIG_ARCH_HAS_TIMING_FUNCTIONS 1
#define CONFIG_ARCH_HAS_TRUSTED_EXECUTION 1
#define CONFIG_ARCH_HAS_STACK_PROTECTION 1
#define CONFIG_ARCH_HAS_USERSPACE 1
#define CONFIG_ARCH_HAS_EXECUTABLE_PAGE_BIT 1
#define CONFIG_ARCH_HAS_RAMFUNC_SUPPORT 1
#define CONFIG_ARCH_HAS_NESTED_EXCEPTION_DETECTION 1
#define CONFIG_ARCH_SUPPORTS_COREDUMP 1
#define CONFIG_ARCH_SUPPORTS_ARCH_HW_INIT 1
#define CONFIG_ARCH_HAS_EXTRA_EXCEPTION_INFO 1
#define CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE 1
#define CONFIG_ARCH_HAS_SUSPEND_TO_RAM 1
#define CONFIG_ARCH_HAS_THREAD_ABORT 1
#define CONFIG_ARCH_HAS_CODE_DATA_RELOCATION 1
#define CONFIG_CPU_HAS_TEE 1
#define CONFIG_CPU_HAS_FPU 1
#define CONFIG_CPU_HAS_MPU 1
#define CONFIG_MPU 1
#define CONFIG_MPU_LOG_LEVEL_INF 1
#define CONFIG_MPU_LOG_LEVEL 3
#define CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS 1
#define CONFIG_MPU_GAP_FILLING 1
#define CONFIG_SRAM_REGION_PERMISSIONS 1
#define CONFIG_TOOLCHAIN_HAS_BUILTIN_FFS 1
#define CONFIG_KERNEL_LOG_LEVEL_INF 1
#define CONFIG_KERNEL_LOG_LEVEL 3
#define CONFIG_MULTITHREADING 1
#define CONFIG_NUM_COOP_PRIORITIES 16
#define CONFIG_NUM_PREEMPT_PRIORITIES 15
#define CONFIG_MAIN_THREAD_PRIORITY 0
#define CONFIG_COOP_ENABLED 1
#define CONFIG_PREEMPT_ENABLED 1
#define CONFIG_PRIORITY_CEILING -127
#define CONFIG_IDLE_STACK_SIZE 320
#define CONFIG_ISR_STACK_SIZE 2048
#define CONFIG_THREAD_STACK_INFO 1
#define CONFIG_ERRNO 1
#define CONFIG_SCHED_DUMB 1
#define CONFIG_WAITQ_DUMB 1
#define CONFIG_BOOT_BANNER 1
#define CONFIG_BOOT_DELAY 0
#define CONFIG_SYSTEM_WORKQUEUE_PRIORITY -1
#define CONFIG_ATOMIC_OPERATIONS_BUILTIN 1
#define CONFIG_TIMESLICING 1
#define CONFIG_TIMESLICE_SIZE 0
#define CONFIG_TIMESLICE_PRIORITY 0
#define CONFIG_NUM_MBOX_ASYNC_MSGS 10
#define CONFIG_KERNEL_MEM_POOL 1
#define CONFIG_ARCH_HAS_CUSTOM_SWAP_TO_MAIN 1
#define CONFIG_SWAP_NONATOMIC 1
#define CONFIG_SYS_CLOCK_EXISTS 1
#define CONFIG_TIMEOUT_64BIT 1
#define CONFIG_SYS_CLOCK_MAX_TIMEOUT_DAYS 365
#define CONFIG_XIP 1
#define CONFIG_KERNEL_INIT_PRIORITY_OBJECTS 30
#define CONFIG_KERNEL_INIT_PRIORITY_DEFAULT 40
#define CONFIG_KERNEL_INIT_PRIORITY_DEVICE 50
#define CONFIG_APPLICATION_INIT_PRIORITY 90
#define CONFIG_STACK_POINTER_RANDOM 0
#define CONFIG_MP_NUM_CPUS 1
#define CONFIG_TICKLESS_KERNEL 1
#define CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE 1
#define CONFIG_CONSOLE 1
#define CONFIG_CONSOLE_INPUT_MAX_LINE_LEN 128
#define CONFIG_CONSOLE_HAS_DRIVER 1
#define CONFIG_CONSOLE_INIT_PRIORITY 60
#define CONFIG_UART_CONSOLE 1
#define CONFIG_UART_CONSOLE_INPUT_EXPIRED 1
#define CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT 15000
#define CONFIG_UART_CONSOLE_LOG_LEVEL_INF 1
#define CONFIG_UART_CONSOLE_LOG_LEVEL 3
#define CONFIG_HAS_SEGGER_RTT 1
#define CONFIG_ETH_INIT_PRIORITY 80
#define CONFIG_SERIAL_HAS_DRIVER 1
#define CONFIG_SERIAL_SUPPORT_ASYNC 1
#define CONFIG_SERIAL_SUPPORT_INTERRUPT 1
#define CONFIG_UART_LOG_LEVEL_INF 1
#define CONFIG_UART_LOG_LEVEL 3
#define CONFIG_UART_USE_RUNTIME_CONFIGURE 1
#define CONFIG_UART_ASYNC_API 1
#define CONFIG_UART_NRFX 1
#define CONFIG_UART_ASYNC_TX_CACHE_SIZE 8
#define CONFIG_UART_0_NRF_UARTE 1
#define CONFIG_UART_0_ENHANCED_POLL_OUT 1
#define CONFIG_UART_0_ASYNC 1
#define CONFIG_UART_0_NRF_TX_BUFFER_SIZE 32
#define CONFIG_UART_0_GPIO_MANAGEMENT 1
#define CONFIG_UART_1_NRF_UARTE 1
#define CONFIG_UART_1_ASYNC 1
#define CONFIG_UART_1_ENHANCED_POLL_OUT 1
#define CONFIG_UART_1_NRF_HW_ASYNC 1
#define CONFIG_UART_1_NRF_ASYNC_LOW_POWER 1
#define CONFIG_UART_1_GPIO_MANAGEMENT 1
#define CONFIG_UART_2_NRF_UARTE 1
#define CONFIG_UART_2_ASYNC 1
#define CONFIG_UART_2_ENHANCED_POLL_OUT 1
#define CONFIG_UART_2_GPIO_MANAGEMENT 1
#define CONFIG_UARTE_NRF_HW_ASYNC 1
#define CONFIG_UART_ENHANCED_POLL_OUT 1
#define CONFIG_NRF_UARTE_PERIPHERAL 1
#define CONFIG_INTC_INIT_PRIORITY 40
#define CONFIG_INTC_LOG_LEVEL_INF 1
#define CONFIG_INTC_LOG_LEVEL 3
#define CONFIG_SYSTEM_CLOCK_INIT_PRIORITY 0
#define CONFIG_TICKLESS_CAPABLE 1
#define CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY 1
#define CONFIG_ENTROPY_LOG_LEVEL_INF 1
#define CONFIG_ENTROPY_LOG_LEVEL 3
#define CONFIG_ENTROPY_INIT_PRIORITY 50
#define CONFIG_ENTROPY_PSA_CRYPTO_RNG 1
#define CONFIG_ENTROPY_HAS_DRIVER 1
#define CONFIG_GPIO_LOG_LEVEL_INF 1
#define CONFIG_GPIO_LOG_LEVEL 3
#define CONFIG_GPIO_NRFX 1
#define CONFIG_FXL6408_LOG_LEVEL_INF 1
#define CONFIG_FXL6408_LOG_LEVEL 3
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL_INF 1
#define CONFIG_CLOCK_CONTROL_LOG_LEVEL 3
#define CONFIG_CLOCK_CONTROL_NRF 1
#define CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL 1
#define CONFIG_CLOCK_CONTROL_NRF_K32SRC_50PPM 1
#define CONFIG_CLOCK_CONTROL_NRF_ACCURACY 50
#define CONFIG_FLASH_HAS_DRIVER_ENABLED 1
#define CONFIG_FLASH_HAS_PAGE_LAYOUT 1
#define CONFIG_FLASH 1
#define CONFIG_FLASH_LOG_LEVEL_INF 1
#define CONFIG_FLASH_LOG_LEVEL 3
#define CONFIG_FLASH_PAGE_LAYOUT 1
#define CONFIG_FLASH_INIT_PRIORITY 50
#define CONFIG_SOC_FLASH_NRF 1
#define CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE 1
#define CONFIG_CRYPTO 1
#define CONFIG_CRYPTO_INIT_PRIORITY 90
#define CONFIG_CRYPTO_LOG_LEVEL_INF 1
#define CONFIG_CRYPTO_LOG_LEVEL 3
#define CONFIG_CRYPTO_TINYCRYPT_SHIM 1
#define CONFIG_CRYPTO_TINYCRYPT_SHIM_MAX_SESSION 2
#define CONFIG_CRYPTO_TINYCRYPT_SHIM_DRV_NAME "CRYPTO_TC"
#define CONFIG_PINCTRL_LOG_LEVEL_INF 1
#define CONFIG_PINCTRL_LOG_LEVEL 3
#define CONFIG_PINCTRL_STORE_REG 1
#define CONFIG_PINCTRL_NON_STATIC 1
#define CONFIG_PINCTRL_DYNAMIC 1
#define CONFIG_PINCTRL_NRF 1
#define CONFIG_MBOX 1
#define CONFIG_MBOX_INIT_PRIORITY 50
#define CONFIG_MBOX_LOG_LEVEL_INF 1
#define CONFIG_MBOX_LOG_LEVEL 3
#define CONFIG_USBC_LOG_LEVEL_INF 1
#define CONFIG_USBC_LOG_LEVEL 3
#define CONFIG_SUPPORT_MINIMAL_LIBC 1
#define CONFIG_PICOLIBC_SUPPORTED 1
#define CONFIG_NEWLIB_LIBC 1
#define CONFIG_HAS_NEWLIB_LIBC_NANO 1
#define CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE 2048
#define CONFIG_NEWLIB_LIBC_FLOAT_PRINTF 1
#define CONFIG_STDOUT_CONSOLE 1
#define CONFIG_NOTIFY 1
#define CONFIG_CRC 1
#define CONFIG_MPSC_PBUF 1
#define CONFIG_ONOFF 1
#define CONFIG_REBOOT 1
#define CONFIG_CBPRINTF_COMPLETE 1
#define CONFIG_CBPRINTF_FULL_INTEGRAL 1
#define CONFIG_CBPRINTF_FP_SUPPORT 1
#define CONFIG_CBPRINTF_N_SPECIFIER 1
#define CONFIG_CBPRINTF_PACKAGE_LOG_LEVEL_INF 1
#define CONFIG_CBPRINTF_PACKAGE_LOG_LEVEL 3
#define CONFIG_SYS_HEAP_ALLOC_LOOPS 3
#define CONFIG_SYS_HEAP_SMALL_ONLY 1
#define CONFIG_MAX_TIMER_COUNT 5
#define CONFIG_PRINTK 1
#define CONFIG_EARLY_CONSOLE 1
#define CONFIG_ASSERT 1
#define CONFIG_ASSERT_LEVEL 2
#define CONFIG_SPIN_VALIDATE 1
#define CONFIG_ASSERT_VERBOSE 1
#define CONFIG_LOG 1
#define CONFIG_LOG_MODE_DEFERRED 1
#define CONFIG_LOG_OVERRIDE_LEVEL 0
#define CONFIG_LOG_MAX_LEVEL 4
#define CONFIG_LOG_PRINTK 1
#define CONFIG_LOG_MODE_OVERFLOW 1
#define CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD 10
#define CONFIG_LOG_PROCESS_THREAD 1
#define CONFIG_LOG_PROCESS_THREAD_STARTUP_DELAY_MS 0
#define CONFIG_LOG_PROCESS_THREAD_SLEEP_MS 1000
#define CONFIG_LOG_PROCESS_THREAD_STACK_SIZE 2048
#define CONFIG_LOG_TRACE_SHORT_TIMESTAMP 1
#define CONFIG_LOG_FUNC_NAME_PREFIX_DBG 1
#define CONFIG_LOG_BACKEND_SHOW_COLOR 1
#define CONFIG_LOG_TAG_MAX_LEN 0
#define CONFIG_LOG_BACKEND_FORMAT_TIMESTAMP 1
#define CONFIG_LOG_BACKEND_UART 1
#define CONFIG_LOG_BACKEND_UART_BUFFER_SIZE 1
#define CONFIG_LOG_BACKEND_UART_AUTOSTART 1
#define CONFIG_LOG_BACKEND_UART_OUTPUT_TEXT 1
#define CONFIG_LOG_BACKEND_UART_OUTPUT_DEFAULT 0
#define CONFIG_LOG_DOMAIN_ID 0
#define CONFIG_LOG_USE_VLA 1
#define CONFIG_LOG_FAILURE_REPORT_PERIOD 1000
#define CONFIG_LOG_OUTPUT 1
#define CONFIG_PM_LOG_LEVEL_INF 1
#define CONFIG_PM_LOG_LEVEL 3
#define CONFIG_PM_POLICY_DEFAULT 1
#define CONFIG_PM_DEVICE_LOG_LEVEL_INF 1
#define CONFIG_PM_DEVICE_LOG_LEVEL 3
#define CONFIG_PM_DEVICE_POWER_DOMAIN 1
#define CONFIG_ENTROPY_DEVICE_RANDOM_GENERATOR 1
#define CONFIG_CSPRING_ENABLED 1
#define CONFIG_HARDWARE_DEVICE_CS_GENERATOR 1
#define CONFIG_COVERAGE_GCOV_HEAP_SIZE 16384
#define CONFIG_TOOLCHAIN_ZEPHYR_0_15 1
#define CONFIG_TOOLCHAIN_ZEPHYR_SUPPORTS_THREAD_LOCAL_STORAGE 1
#define CONFIG_LINKER_ORPHAN_SECTION_WARN 1
#define CONFIG_HAS_FLASH_LOAD_OFFSET 1
#define CONFIG_LD_LINKER_SCRIPT_SUPPORTED 1
#define CONFIG_LD_LINKER_TEMPLATE 1
#define CONFIG_KERNEL_ENTRY "__start"
#define CONFIG_LINKER_SORT_BY_ALIGNMENT 1
#define CONFIG_SRAM_OFFSET 0x0
#define CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT 1
#define CONFIG_LINKER_LAST_SECTION_ID 1
#define CONFIG_LINKER_LAST_SECTION_ID_PATTERN 0xE015E015
#define CONFIG_SIZE_OPTIMIZATIONS 1
#define CONFIG_COMPILER_COLOR_DIAGNOSTICS 1
#define CONFIG_FORTIFY_SOURCE_COMPILE_TIME 1
#define CONFIG_COMPILER_OPT ""
#define CONFIG_RUNTIME_ERROR_CHECKS 1
#define CONFIG_KERNEL_BIN_NAME "zephyr"
#define CONFIG_OUTPUT_STAT 1
#define CONFIG_OUTPUT_DISASSEMBLY 1
#define CONFIG_OUTPUT_PRINT_MEMORY_USAGE 1
#define CONFIG_BUILD_OUTPUT_BIN 1
#define CONFIG_WARN_DEPRECATED 1
#define CONFIG_EXPERIMENTAL 1
#define CONFIG_ENFORCE_ZEPHYR_STDINT 1
#define CONFIG_COMPAT_INCLUDES 1

What do I need to do to get this working?

[Øivind]

Hi,

Are you using custom boards for these tests, or are you currently testing with DKs?
Are you using the DK board files found in the SDK, or custom board files?
Which pins on the nRF5340 are you using for LPUART?
Could I see any overlay files or other changes to the devicetree you have made?

My first thought is that the difference between the nRF52840 and the nRF5340 is the default setup for the pin.
Some pins may require an extra step to be changed from their default configuration.

[Chris Burns]

This is on a custom board with custom board files. I created the DTS files for both the board with the nRF52840 and the board with the nRF5340.

The pins wired between the two microcontrollers (on the nRF5340 side) are:

0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, 0.20, 0.21

After your comment I checked the product spec and noticed several of these pins are dedicated QSPI pins, so I changed the DTS to set the QSPI peripheral to "disabled" (from "okay"). This didn't change the result - I still get the unhandled interrupt.

For another test I changed the REQ and RDY pins to be some of the ones that aren't connected to QSPI. The result is the same - ZEPHYR FATAL ERROR 1: Unhandled interrupt on CPU 0.

Again, for both of these tests the error occurs when the nRF9160 attempts to send something and it looks to be tied to the REQ pin on the nRF5340 going high.

Here are the relevant sections from the DTS file:

&gpiote {
    status = "okay";
    interrupts = <13 NRF_DEFAULT_IRQ_PRIORITY>;
};

&uart1 {
    status = "okay";
    current-speed = <460800>;
    pinctrl-0 = <&lpuart_uart1_default>;
    pinctrl-1 = <&lpuart_uart1_sleep>;
    pinctrl-names = "default", "sleep";

    lpuart: nrf-sw-lpuart {
        compatible = "nordic,nrf-sw-lpuart";
        status = "okay";
        req-pin = <14>;
        rdy-pin = <16>;
    };
};

And in the pinctrl DTSI file:

lpuart_uart1_default: lpuart_uart1_default {
    group1 {
        psels = <NRF_PSEL(UART_TX, 0, 13)>,
                    <NRF_PSEL(UART_RX, 0, 15)>;
    };
};

lpuart_uart1_sleep: lpuart_uart1_sleep {
    group1 {
        psels = <NRF_PSEL(UART_RX, 0, 13)>,
                    <NRF_PSEL(UART_TX, 0, 15)>;
        low-power-enable;
    };
};

[Chris Burns]

Additional info: any GPIO interrupts, even if they're not related to LPUART, cause the "Unhandled interrupt" error if I have the interrupts line in gpiote in the DTS file:

&gpiote {
    status = "okay";
    interrupts = <13 NRF_DEFAULT_IRQ_PRIORITY>;
};

If I remove (or comment out) the interrupts line above then GPIO interrupts work normally.

[Øivind]

I started looking into the gpiote after your latest update, apologies for not posting a response.
How are you setting up your gpiote handlers? Could I see the code where you call nrfx_gpiote_input_configure etc.? Do you get the error if you keep the interrupts line, but never call any gpiote functions?

Could you try changing the RX and TX pins to pins which are not by default qspi pins as well?
And I assume that the pins being swapped in default vs sleep is not intentional?
How many gpiote callbacks are you setting up? There is a config you should adjust if you require more than 2 handlers:

CONFIG_NRFX_GPIOTE_NUM_OF_EVT_HANDLERS=2

[Chris Burns]

It looks to me like nrfx_gpiote_input_configure is called by the LPUART driver. In NCS v2.3.0 I see it called in the functions req_pin_init and rdy_pin_init.

As for the pins being swapped I've already corrected that but it doesn't affect the behavior.

If I have the GPIOTE interrupt cell in the DTS but generate no GPIO interrupts the fatal error does not occur. The fatal error occurs when:

• a GPIO configured as an interrupt input,
• the interrupts line for GPIOTE in the DTS, and
• that GPIO line triggers the interrupt.

Unfortunately the board does not have 4 non-QSPI pins wired to the nRF9160. The pins I listed previously are the only ones connected between the two chips. I have tried with the REQ and RDY pins being non-QSPI pins, and with QSPI disabled in the DTS and neither changed the behavior.

Changing the prj.conf to include CONFIG_NRFX_GPIOTE_NUM_OF_EVT_HANDLERS=10 didn't change the behavior.

In case the GPIOTE IRQ wasn't being connected I tried adding this line to my code:

    IRQ_CONNECT(DT_IRQN(DT_NODELABEL(gpiote)),
                DT_IRQ(DT_NODELABEL(gpiote), priority),
                nrfx_isr, nrfx_gpiote_irq_handler, 0);

But it creates this build error:

gen_isr_tables.py: error: multiple registrations at table_index 13 for irq 13 (0xd)
Existing handler 0x1e063, new handler 0x1e063
Has IRQ_CONNECT or IRQ_DIRECT_CONNECT accidentally been invoked on the same irq multiple times?

It also looks like nrfx_gpiote_irq_handler isn't being called. If I add a function call to set an LED in this routine it doesn't turn on.