nrf_gpio_pin_set causes random MCU resets during Manual-CS SPI transactions

[kobyatom]

I created a function, spi_read, that performs a SPI transaction to RAM, comprised of 400 chunks, each 96 bytes long.

The CS control is set to manual.

that function crashes every 5-30 runs, randomly, probably at the call to nrf_gpio_pin_set.

Please see its code below.

As a patch, I added a 1 microsecond wait after nrf_gpio_pin_set, which occurs after every chunk, which solves the issue,

If the PATCH segment is removed, the reset occurs randomly, every 5-30 runs.

I'm using the NRF52840, running SDK version 17.0.2.

astatus_t spi_read(const hal_spi_t * p_spi, uint16_t len, uint8_t reg_add, uint8_t * p_read_buf)
{
    astatus_t rc = AE_SUCCESS;
    spi_xfer_done = false;
    nrfx_spim_xfer_desc_t const tx_xfer_desc = NRFX_SPIM_XFER_TX(&reg_add, 1);
    nrf_gpio_pin_clear(p_spi->spi_manual_cs);
    if ( NRFX_SUCCESS != nrfx_spim_xfer(&m_spi_master[p_spi->spi_index], &tx_xfer_desc, 0) )
    {
        NRF_LOG_ERROR("atom_hal_spi_read_write nrfx_spim_xfer");
        rc = AE_FAILURE;
    }
    if (AE_SUCCESS == rc)
    {
        rc = wait_for_spi_completion(OP_TIMEOUT_MSEC);
    }
	if ( rc != AE_SUCCESS )
    {
        ATLOG_WARN("wait_for_spi_completion failed %d", rc);
        goto hal_spi_read_exit;
    }

    nrfx_spim_xfer_desc_t const rx_xfer_desc = NRFX_SPIM_XFER_RX(p_read_buf, len);
    spi_xfer_done = false;
    if ( NRFX_SUCCESS != nrfx_spim_xfer(&m_spi_master[p_spi->spi_index], &rx_xfer_desc, 0) )
    {
        NRF_LOG_ERROR("atom_hal_spi_read_write nrfx_spim_xfer");
        rc = AE_FAILURE;
    }
    if (AE_SUCCESS == rc)
    {
        rc = wait_for_spi_completion(OP_TIMEOUT_MSEC);
    }
hal_spi_read_exit:
    nrf_gpio_pin_set(p_spi->spi_manual_cs);
    
    /////////// PATCH
    atom_hal_time_delay_us(1);
    /////////// PATCH
    return rc;
}

How can I better solve this?

[kobyatom]

we carefully implemented this reset-reason feature a few months ago, and verified it to work with reset reasons SREQ and RESETPIN.

Here is the implementation:

We have a static member that gets the reset reason on init, from the RESETREAS reg

const uint32_t reset_reason = nrf_power_resetreas_get();    // Do before any other action https://devzone.nordicsemi.com/f/nordic-q-a/48446/how-to-detect-cause-of-reset

in main() we clear the resetreas register

nrf_power_resetreas_clear(NRF_POWER_RESETREAS_OFF_MASK);    // Clear this register, instead of the bootloader.

and later we print the previously saved reset reason

ATLOG_INFO("reset_reason 0x%08x", reset_reason);

[Susheel Nuguru]

I have never seen before that the reset reasons reads 0 before clearing up the register. Can you help me reproduce your error. Maybe give me a simplistic project where I can see the same reset and same reset reason 0 as you see (when the delay is not added)

[kobyatom]

thanks, I will try 

[kobyatom]

the SPI is read via APP_SCHED, not from the ISR.

I don't know how easy it will be to reproduce, since my ISR source is external - an Accelerometer that generates an interrupt every 16 samples (each 6 bytes long), with a sample rate of 3200 Hz (5 msec between interrupts).

[kobyatom]

anyway, reset_reas value is 0 on powerup...
so maybe there is a power drop issue on my circuit, due to some contention on the SPI + CS lines.