Essential pin planning guidelines for the nRF54L Series

Efficient pin planning is a critical first step in any successful embedded system design, especially when power consumption and flexibility are key. Properly assigning the SoC’s available pins to various peripherals is crucial for ensuring not only correct operation but also maintaining ultra-low-power operation. While the nRF54L Series offers flexibility in routing peripheral signals to pins, this flexibility operates within a defined structure optimized for low-power efficiency.

In this blog post, we will explore the essential aspects of pin planning for the nRF54L Series (nRF54L15, nRF54L10, nRF54L05). We'll begin by exploring the power domains and their associated GPIO ports relevant to pin planning. We'll highlight the number of pins available from each domain and their key characteristics, such as speed limitations and support for features like pin sense, GPIOTE, and the ability to wake the system from sleep. 

Then, we will examine the available SoC packages and discuss the most important rules and constraints governing pin assignments on the nRF54L Series. To wrap up, we’ll introduce a helpful open-source pin-planning tool for the nRF54L Series (QFN-48 package).

Power domains on the nRF54L Series

Pin planning involves peripherals that require pins, such as ADC, PWM, SPI, UART, etc. To effectively map a peripheral to the correct pins, we need to know which domain it belongs to.

Definition: A power domain is a section of a chip that can be independently powered on or off to optimize energy consumption.

The nRF54L Series architecture is divided into four power domains.

0. MCU domain (MCU): This domain houses the Arm Cortex-M33 processor, a RISC-V coprocessor as a fast, lightweight peripheral processor (FLPR), and a debug system including ETM trace. It also contains high-speed peripherals (e.g., UARTE and HS-SPI). The MCU domain operates on a 128 MHz clock. Peripherals in this domain that have a numeric ID will start with the number 0 (e.g., UARTE00). This domain has a dedicated GPIO port, which is port 2 (P2).

1. Radio domain (RADIO): This domain contains the short-range radio and peripherals that support the radio protocol stack. It runs at 32 MHz, and since all the peripherals inside it are meant to support the radio, this domain does not have a dedicated GPIO port. This domain is not relevant for pin planning (except when direction finding or multi-antenna channel sounding is used—see rule 4.f).  

2. Peripheral domain (PERI): This domain contains most of the peripherals on the chip, and operates at 16 MHz. Peripherals in this domain that have a numeric ID will start with the number 2 (e.g., UARTE20). This domain has a dedicated GPIO port, which is port 1 (P1).

3. Low-power domain (LP): This domain is dedicated to peripherals designed for ultra-low power modes. It can be used to wake up the rest of the system even if the peripheral domain is powered off. It runs at 16 MHz, and peripherals in this domain that have a numeric ID will start with the number 3 (e.g., UARTE30).  This domain has a dedicated GPIO port, which is port 0 (P0)

The following block diagram shows the available power domains and their components and peripherals.  

One key reason for implementing an SoC with multiple power domains is to ensure low-power operation. By allowing domains to be powered independently, large sections of the chip can be turned off when not actively needed, which helps achieve lower power consumption. This enables improved battery lifetime and reduced battery size. The low-power domain, in particular, contains peripherals specifically designed for ultra-low power modes and can wake the rest of the system even when the peripheral domain is powered off.

Available ports & features

Three of the power domains, MCU, PERI, and LP, have their own GPIO ports (P2, P1, and P0, respectively), while the RADIO domain does not. P1 and P0 have many similarities, while P2 differs significantly. Let’s take a look at the features of each of these ports.

• GPIO port 2 (P2): This port is associated with the MCU domain.
  • The number of pins on this port depends on the package used. For the QFN-48 package, there are 11 pins: P2.00 to P2.10
  • Pins on this port are the fastest on the chip and intended for high-speed signals such as trace or fast serial communication.
  • The maximum speed for signals on P2 is 64 MHz.
  • Supports standard, high drive, and extra high drive.
  • P2 pins cannot wake the system from sleep, and it does not include the GPIO SENSE or DETECT mechanism or GPIOTE functionality. This means that interrupt support is not available on P2 pins when they are configured as general-purpose GPIO.
  • Peripherals located in the MCU domain, such as SPIM00 and UARTE00, use dedicated pins on P2.
  • Dedicated pins for TRACE and FLPR (for emulated peripherals like QSPI) are also on P2.
  • Selected pins on P2 can also be used by certain serial interfaces (SPIM, SPIS, UARTE) located in the peripheral domain, although this configuration is considered less power-efficient.
• GPIO port 1 (P1): This port is associated with the PERI domain
  • The number of pins on this port depends on the package used. For the QFN-48 package, there are 15 pins: P1.00-P1.14.
  • The maximum speed for signals on P1 is 8 MHz.
  • Supports standard and high drive only.
  • P1 pins can wake the system up from System ON or System OFF sleep.
  • Includes analog input pins (AIN0-AIN7), which are shared by the ADC (SAADC) and the COMP/LPCOMP in the LP domain.
  • PWM peripherals are only available on P1 pins.
  • P1 supports the pin sense mechanism and is associated with GPIOTE20.
  • Dedicated pins for TAMPC when tamper detection is used.
  • Dedicated RADIO pins are on P1 when direction finding or channel sounding multi-antennas are used.
  • Dedicated NFC antenna pins on P1 configured as NFC antenna pins from reset. These can be changed as general-purpose GPIO.
• GPIO port 0 (P0): This port is associated with the LP domain.
  • The number of pins on this port depends on the package used. For the QFN-48 package, there are 5 pins: P0.00-P0.04
  • The maximum speed for signals on P0 is 8 MHz.
  • Supports standard and high drive only.
  • P0 pins can wake the system up from System ON or System OFF sleep.
  • P0 supports the pin sense mechanism and is associated with GPIOTE30.
  • Dedicated pins for GRTC when its clock and PWM output is used.

The following diagram describes the peripherals on each power domain as well as their corresponding GPIO ports, for the QFN-48 package.

nRF54L QFN-48: Power domains and GPIO ports

Summary of port capabilities

Available packages

Below are the available packages for the nRF54L Series (nRF54L15/10/05) at the time of publishing this blog post.

Essential pin planning rules

1. Match peripherals to their domains: Generally, peripherals must use pins in their own power domain.

However, there are some exceptions:

a.      COMP/LPCOMP in the LP domain must use the analog pins in P1.
b.      Selected pins on P2 can also be used by certain serial interfaces (SPIM, SPIS, UARTE) located in PERI, although this configuration is less power-efficient.
c.      GRTC in the PERI has dedicated pins on P0 when its clock and PWM output are used.

2. Dedicated clock pins: Some peripherals with clock signals (like SPI, TWI, and TRACE) require the use of specific dedicated clock pins. These pins are optimized for timing and are marked with a cross in the pin assignment tables. All peripherals with clock signals must use these dedicated pins.

3. General-purpose GPIO usage: All port pins can be used as GPIO pins. However, P2 pins do not support Sense/DETECT or GPIOTE functionality.

4. Dedicated pin assignments: Certain peripherals have dedicated pins that they must use

a.      FLPR: dedicated pins on P2.
b.      SPIM00/UARTE00: dedicated pins on P2.
c.      GRTC: dedicated pins for clock and PWM output (if used) on P0. Dedicated pin for CLK16M on P1 (if used).
d.      TAMPC: dedicated pins on P1.
e.      NFC: dedicated pins on P1.
f.      RADIO: dedicated pins on P1 (DFEGPIO Pins), these pins are only needed when direction finding or channel sounding multi-antennas are used

5. Fixed-function pins: There are a few fixed-function pins on all packages (non-GPIO pins). These pins have a fixed function that can’t be changed: (power and ground, crystal oscillator pins, decoupling and regulator pins, RF antenna pin (ANT pin), reset pin, and Serial Wire Debug).

nRF54L Pin Planner web tool

One of our field application engineers created a proof-of-concept pin planning utility for the nRF54L15/10/05 to better manage power domain and peripheral requirements, starting with the QFN-48 package. This tool encodes all valid pin-to-peripheral mappings and keeps a running list of pins already used to prevent misconfiguration. It also tracks which peripherals require clock pins and ensures that they are properly used.

This project is open source, with an MIT license, and can be found here: https://hlord2000.github.io/

If you have feedback, questions, or suggestions about this tool, please open an issue at GitHub - hlord2000/hlord2000.github.io: Helmut's personal site. Or leave a comment on this post. Pull requests are also welcome.

Closing

Effective pin planning is important for utilizing the full potential of the nRF54L Series while maintaining ultra-low power. By understanding the structure of power domains, the capabilities of each GPIO port, and the peripheral mapping rules, you can make an informed decision that prevents conflicts and ensures system efficiency. The nRF54L Pin Planner web tool provides a practical way to streamline this process. We invite you to explore the tool, contribute feedback, or open a pull request to help improve it. As always, careful planning up front can save countless hours in development and debugging down the line.

References

• 10-Hardware and layout -> 10.1-Pin assignments in nRF54L15 | nRF54L10 | nRF54L05 Preliminary Datasheet (released in May 2025)
  • Note that the Pin assignments section now has specific assignments for UARTE00 in P2. Previous versions allowed for any P2 pin to be used for UARTE00