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Memory Protection and PinReset Configuration with OpenOCD

I am trying to set the Memory protection bit and PinReset configuration with OpenOCD. I have applied the NRF52 patch (outlined here: devzone.nordicsemi.com/.../ )

I am able to program .hex files to an NRF52 after running nrfjprog --recover -f nrf52. However, I need to 'recover' with OpenOCD. I tried Michael Dietz's solution without success.

This answer concerning the APPROTECT leads me to believe that there may be a step missing in Michael's answer - the SWDWriteDP 1 0x50000000 -> Enable power (as suggested by Segger response) is not run, and I'm not sure how to perform that with OpenOCD.

From what I understand, there is nothing specific to the NRF52 for the Memory Protection or PinReset. The dap process should work, but I can't get it to. I must be missing something obvious, and any help would be appreciated.

Has anyone been able to set both the Memory Protection AND Enable PinReset with OpenOCD for the NRF52? If so could you please let me know how? (or what I am missing)

Edit: Here is the console output.

pi@raspberrypi:~/nordic $ Open On-Chip Debugger 0.10.0+dev-00092-g77189db-dirty (2017-03-03-15:04)
Licensed under GNU GPL v2
For bug reports, read
	openocd.org/.../bugs.html
BCM2835 GPIO nums: swclk = 25, swdio = 24
BCM2835 GPIO config: srst = 18
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
adapter speed: 10000 kHz
cortex_m reset_config sysresetreq
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
adapter_nsrst_delay: 100
adapter_nsrst_assert_width: 100
adapter speed: 1000 kHz
Info : BCM2835 GPIO JTAG/SWD bitbang driver
Info : SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)
Info : clock speed 1001 kHz
Info : SWD DPIDR 0x2ba01477
Error: Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* nrf52.cpu          cortex_m   little nrf52.cpu          unknown
Error: Could not find MEM-AP to control the core
Error: Target not examined, will not halt after reset!
TARGET: nrf52.cpu - Not halted
in procedure 'reset' called at file "openocd.cfg", line 17
in procedure 'ocd_bouncer'



pi@raspberrypi:~/nordic $ telnet localhost 4444
Trying ::1...
Trying 127.0.0.1...
Info : accepting 'telnet' connection on tcp/4444
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> dap apreg 1 0x04
0x00000000
          0x00000000
> dap apreg 1 0x04 0x01
> dap apreg 1 0x040x00000001

0x00000001

FULL POWER RESET HERE

> dap apreg 1 0x04
0x00000000
          0x00000000
> exit
Connection closed by foreign host.
Info : dropped 'telnet' connection
pi@raspberrypi:~/nordic $ sudo pkill openocd
[1]+  Exit 143                sudo openocd
pi@raspberrypi:~/nordic $ sudo openocd &
[1] 3634
pi@raspberrypi:~/nordic $ Open On-Chip Debugger 0.10.0+dev-00092-g77189db-dirty (2017-03-03-15:04)
Licensed under GNU GPL v2
For bug reports, read
	openocd.org/.../bugs.html
BCM2835 GPIO nums: swclk = 25, swdio = 24
BCM2835 GPIO config: srst = 18
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
adapter speed: 10000 kHz
cortex_m reset_config sysresetreq
srst_only separate srst_gates_jtag srst_push_pull connect_deassert_srst
adapter_nsrst_delay: 100
adapter_nsrst_assert_width: 100
adapter speed: 1000 kHz
Info : BCM2835 GPIO JTAG/SWD bitbang driver
Info : SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)
Info : clock speed 1001 kHz
Info : SWD DPIDR 0x2ba01477
Error: Could not find MEM-AP to control the core
    TargetName         Type       Endian TapName            State
--  ------------------ ---------- ------ ------------------ ------------
 0* nrf52.cpu          cortex_m   little nrf52.cpu          unknown
Error: Could not find MEM-AP to control the core
Error: Target not examined, will not halt after reset!
TARGET: nrf52.cpu - Not halted
in procedure 'reset' called at file "openocd.cfg", line 17
in procedure 'ocd_bouncer'

Edit: I'm taking another look at the product specification, Section 16 (page 70), Debug and Trace. It indicates "Before the external debugger can access the CPU's access port (AHB-AP) or the Control Access Port (CTRL-AP), the debugger must first request the device to power up via CxxxPWRUPREQ in the SWJ-DP.", but doesn't say HOW to set CxxxPWRUPREQ. I assume I'm writing 0x01 to CxxPWRUPREQ (which follows with the links previously provided), but again, I don't know how to access the SW-DP->CxxxPWRUPREQ

Edit 2: The CxxxPWUPREQ appears to be CSYSPWRUPREQ and CDBGPWRUPREQ. "To initiate powerup, CxxxPWRUPREQ must be asserted HIGH by the Debug Port." The CxxxPWUPREQ exist as bytes within the CTRL/STATUS register of the dap. See the Arm Debug Interface section 2.3.2 (page 47). So now I need to figure out: 1. How t read the ctrl/stat register, 2. How to write the ctrl/stat register.

Edit 3: According to this, "The Control/Status Register is always present on all debug port implementations...It is located at address 0b01 on read and write operations when the APnDP=b1 and the CTRLSEL=b0 in the Select Register." I need to write 0x50000000 to the CTRL/STATUS register. That sets bits [30], [28] to 1 (which are CSYSPWRUPREQ and CDBGPWRUPREQ respectively). I'm going around in circles.

Edit 4: The patch that I applied to openocd was incomplete. I will post an answer once I am able to fully replicate what was done to get it working

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